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Latest community activity
March 17, 2025
●ABAX
asked a question in28 minutes agoKeil Interface with FPGA for ARM Debugging
ARM processor fpga prototyping setup needs to be connected to Keil. 1- How to configure ARM IP (SSE710 or others) 2- How to wire from ARM processor to FPGA pins 3- Which interface board needs to be connected to the FPGA pins 4- How to connect to the Keil...
Streamlining software migration in automotive systems with Arm and INCHRON
Arm and INCHRON's collaborative model-based simulation methodology addresses challenges in migrating automotive software to Software-Defined Vehicles (SDVs).ACE：why writeunqiue/writelineunqiue cant overlap with writeback？
writeunqiue/writelineunqiue may cause a interconnection snoop，and if all master can answer a snoop（need data）back from snoop data(cd) channel，then when cant writeunqiue/writelineunqiue overlap with writeback？
I knwon it is forbidden becase this may cause...
about 13 hours ago
It is due to a potential deadlock - references below are to the AXI.H.c Specification.
An ACE manager is allowed to delay responding to snoop until a WriteBack completes (D5.2.3). In some cases, the ACE managers only choice is to delay responding to the snoop as it would need to invalidate the line (for example, with a ReadUnique snoop) - see the same reference as above. If it does delay the response, then it potentially causes ordering/coherency issues.
However, an ACE manager is not allowed to delay responding to snoop until a WriteUnique it has issued completes. .
If the WriteBack was physically blocked behind the WriteUnique, and the manager was not able to respond to a snoop then you would have a deadlock as the WriteUnique might require the snoop to progress in order for the WriteBack to make progress.
Using some addresses as an example:
- M0 issues a WriteUnique to 0x10_0000
- M0 issues a WriteBack to 0x20_0000
- M0 receives an invalidating snoop to 0x20_0000
- M0 receives a snoop to 0x10_0000
- M0 cannot respond to snoop 0x20_0000 until the WriteBack completes.
- The WriteBack requires the WriteUnique to make progress in order to complete.
- The WriteUnique cannot complete as it would be address hazarding on the transaction that caused the snoop to 0x10_0000, and that requires the snoop to 0x10_0000 to complete.
- The snoop to 0x10_0000 cannot complete until the snoop to 0x20_0000 completes.
- Deadlock.
Answer a question that is verified as helpful or correct.
●훈상 이
asked a question in11 days agoMDK-ARM V5.42 Installation Error
MDK-ARM V5.42 Installation Error
There is a problem where the installation does not proceed after an error message like the image is displayed during installation.
How can I solve this?
You're right. The current solution is a temporary workaround. In the next release, we plan to improve this by, for example, changing the file name to English only. However, it will take a few weeks for the release to be available. If this solution doesn’t work for you, we recommend continuing to use the previous version of µVision. Thank you for your understanding.
How to mapping MSI (LPIs) in Linux kernel 6.12.y ?
Hello everyone,
I am experiencing an issue with dummy device driver(for test) based on kernel-6.12.y
The problem occurs during the call to devm_request_irq()
Issue Description:
The dummy device node in the device tree is configured to use ITS-based MSI...
Thank you for coming back to share the solution you discovered with the community.
MDK-Middleware 8.0.0 ETH cannot communicate at 10Mbps
Hello.
We have updated the pack from 7.16.0 to MDK 8.0.0.
When connecting Eth via RMII with auto-negotiation enabled, ping works at 100 Mbps, but we are experiencing an issue where ping does not communicate at 10 Mbps.
Our investigation suggests that...
about 12 hours ago
In MDK 8.0.0 the EMAC control has not changed, but the Ethernet driver for STM32H743 has. Did you use the EMAC Ethernet driver from the CMSIS_Driver_STM32 pack? Please provide more information.
Multi-Master APB Subsystem
Hi,
Typically, APB is introduced with a single master (e.g. AHB/APB bridge). My question whether we can have multi-master APB system or not. From APB specifications, i don't see any limitation. Can someone elaborate on this point?
Thanks
Can you help?
Keil Interface with FPGA for ARM Debugging
Not answered 28 minutes ago
MDK-Middleware 8.0.0 ETH cannot communicate at 10Mbps
Not answered about 22 hours ago
Multi-Master APB Subsystem
Not answered 1 day ago