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CADENCE INCISIVE FUNCTIONAL VERIFICATION PLATFORM
RTL (Front End) Tools
INCISIVE VERIFICATION PLATFORM
Cadence collaborates with ARM on offering a complete verification platform for customers developing SoC design using ARM processors. This complete solution addresses the most demanding needs of today’s designers, starting with system-level verification right through to hand-off for physical design.
The key components of the platform include a set of tools to support block-, chip-, and system-level verification; flows to address key design challenges such as low-power verification and metric-driven verification, and a methodology based on the standard OVM that allows customers to build powerful, open, and reusable verification environments.
Tools in the Incisive Platform include:
Incisive Enterprise Manager Automates and guides verification from planning to closure. Includes SystemVerilog and e functional coverage capabilities.
Incisive Enterprise Simulator – XL supports simulation of the design and testbench using all standard languages available today: Verilog, SystemVerilog, e, SVA, VHDL, SystemC, C/C++, and PSL.
Incisive Formal Verifier performs formal analysis in the assertion-based verification and debug of RTL block designs, before testbench availability, to speed design convergence.
Incisive Palladium and Xtreme enables simulation acceleration and emulation of sub-systems and SoCs.
Incisive Verification IP supports advanced testbenches, transaction-based acceleration for high-level testbenches, assertion-based VIP for formal, simulated, and accelerated block-level verification, and emulation and in-circuit verification. Supports ARM-based protocols such as AXI, AHB, and APB.