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True Circuits, Inc. develops and markets a broad range of award-winning PLLs, DLLs and other mixed-signal hard macros for ICs for the semiconductor, systems and electronics industries. TCI's robust state-of-the-art circuits, methodical and proven design strategy and its close association with the world's leading silicon fabrication vendors, allow the company to quickly and reliably create new and innovative designs in a variety of advanced process technologies.
TCI's complete family of standardized general purpose, clock generator, deskew, and spread-spectrum PLLs and DDR DLLs spans nearly all performance points and features typically requested by ASIC, FPGA and SoC designers. These high-quality, low-jitter, silicon-proven timing hard macros are available for immediate delivery in a range of frequencies, multiplication factors, sizes and functions in TSMC, GlobalFoundries, UMC and Common Platform processes from 180nm to 28nm.
General Purpose PLL Features
- Designed as a wide range clock multiplier with deskew capability.
-Delivers optimal jitter performance over all multiplication settings.
- Low area and low power.
- Suitable for system clock, DDR and general purpose applications.
- Ideal for cost sensitive applications.
Clock Generator PLL Features
- Designed as a very flexible clock multiplier capable of multiplying an input clock from 1 to 4096 with very small period jitter while operating at the highest possible bandwidth.
- Delivers optimal jitter performance over all multiplication settings.
- Available with multi-phase outputs and, in some processes, with an I/O voltage regulator.
- Ideal for system clock generation, SerDes and video clock applications.
Spread Spectrum PLL Features
- Designed for PC, networking, and consumer-electronics applications where spread-spectrum clock sources are required to satisfy FCC requirements for peak RF spectral emissions.
- Spreading rate and spreading depth are precisely adjustable to allow the designer to dial-in the desired characteristics.
- 15-bit fractional-N feedback divider with 4 bits of precise control.
- Available with multi-phase outputs.
Deskew PLL Features
- Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
DDR DLL Features
- Designed for high-speed DDR style interface applications.
- Generates precise delays that can be programmed from 0 to 360 degrees of the reference period.
- Delays multiple periodic or aperiodic signals independent of voltage and temperature.
- Optionally outputs multi-phase clocks directly from the reference clock.
- Delivers optimal jitter performance over a wide frequency range.
- Available in flexible form factors for easier integration.