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CHAINworks Self-timed on-chip interconnect EDA tool.
Silistix utilizes breakthrough synthesis technology to generate self-timed on-chip interconnect networks that:
- Reduce design effort
- Promote reuse
- Lower power consumption
A suite of tools named CHAINworks™ fits into existing COT design flows and provides tools for the design and synthesis of on-chip interconnect topologies into a structural netlist.
Reduced design effort
CHAINworks reduces design effort by allowing timing closure to be achieved much quicker than is typically accomplished using conventional synchronous busses. Designs can also be easily scaled for successive product generations.
Multi-protocol support enables CHAIN fabrics to interface with existing peripherals and synchronous bus architectures. Support for AMBA AHB and APB is available with AXI and OCP-IP support soon to follow.
Reduced Power Consumption
CHAIN fabrics reduce power at both the system and interconnect levels. System power is reduced by eliminating frequency balancing issues inherent in synchronous bus architectures utilizing multiple clock domains. Indeed, CHAIN fabrics support any number of unrelated clock domains allowing blocks and subsystems to operate at the lowest frequency possible.
Power consumed by CHAIN fabrics is much lower than that consumed by conventional busses as a result of the self-timed nature of the circuits synthesized by CHAINworks. Shorter wires between the stages of the pipelined CHAIN interconnect further reduce power while self-timed circuits significantly reduce system level clock distribution issues.
CHAIN interconnects synthesized by CHAINworks can be organized in any topology necessary to meet performance requirements. As the fabric is self-timed, it does not require a system clock thereby allowing data to flow between the stages of the fabric as fast as possible rather than waiting on a clock edge. Furthermore, power consumption is dictated by bus traffic rather than clock edges making CHAIN fabrics very low power.
The network nature of CHAIN interconnects allows additional initiators and targets to be added with ease without forcing a redesign of the the entire architecture. Also, data is sent in packets which are routed efficiently through the network per the user-defined topology with user-defined link widths. In this way designers can control the efficiency of data transmission and eliminate system bottlenecks. Likewise, designers have the ability of managing the balance between the area and power consumed of the interconnect.
For more information, please go to our website. www.silistix.com