HVC 710 SV is an APB protocol monitor/checker implemented in SystemVerilog. HVC 710 SV is fully compliant to ARM AMBA3 APB
Specification.
15 APB protocol checks are implemented in HVC 710 SV as SVA properties. According to APB functionality properties implemented in
HVC 710 SV can be grouped like this:
• Signal Testing – 9 properties
• Signal Retraction Testing – 3 properties
• Phase-Based Checks – 3 properties
• Low Power Retraction – 2 properties
• Other Checks – 2 properties
Usage model for HVC 710 SV and it's place in complex testbench is compliant to and defined by Mentor Graphics Advanced Verification
Methodology (AVM).