The Hi3110 is a series of highly-integrated single-chip decoders. They provide cost-effective solutions for both set top box (STB) and DTV. These solutions reduce both the chip cost and overall BOM cost.
The Hi3110 has an embedded ARM9 CPU with a performance of 220 MIPS at 216 MHz. The ARM9 runs the software platform including CA and middleware. In addition, the ARM9 also schedules the internal modules, and processes the scheduling of each module.
The Hi3110 supports MPEG MP@ML video decoding and is compatible with MPEG1 code stream. It gives the Hi3110 multi-level fault tolerance capability and video programmable zooming. The Hi3110 supports the audio encoding of MPEG2 Layer I, MPEG2 Layer II, MPEG1 Layer I and MPEG1 Layer II. The chip provides two SmartCard interfaces to implement the STB CA.
The Hi3110 is embedded with multiple DACs to support audio analog output and video analog output. The related audio digital interfaces are also provided.
The Hi3110 supports complex OSG hardware acceleration for high-quality OSD picture.
The Hi3110 provides an infrared port to control the STB. It also provides a serial port and 4 pairs of 8-bit GPIO control ports for debugging and control (Two of the GPIO control ports are duplex with the other ports).