ANSI-C programmable, extremely parallel, yet low-cost embedded communications processor is optimized for complex algorithms, particularly for OFDM (wireless) applications.
The scalable architecture computes up to 4 sustained complex multiply-accumulates (MACs) or FFT butterflies per cycle. It executes up to 22x32 bits (or 52x16 bits) operations in parallel. For a typical configuration supporting DVB-T, ~250K NAND2-equivalent logic gates suffice (2 complex MACs, 6 complex load/stores, 2 complex shifts, etc.). The processor is characterized for 200 MHz.