RTL designers need to make decisions that impact the timing and physical feasibility of a chip during the downstream implementation flow. Since RTL designers have limited visibility into physical implementation, the impact of these decisions are resolved late in the process. The result can be several iterations between back-end and front-end designers, a costly problem.
The SpyGlass® Physical Base solution provides early estimates of area, timing and routability for RTL designers without the need for physical design expertise or tools. It provides high value physical reports and rules to identify area, congestion and timing issues at early stages of the design. With the SpyGlass-Physical solution, RTL designers can make sure RTL blocks will be easier to implement and reduce SoC design closure time.