Liberate is an ultra-fast standard cell and I/O library models creator. It generates electrical cell views for timing, power and signal integrity including advanced current source models (CCS and ECSM). It uses a unique “inside view” approach where each cell undergoes a pre-characterization circuit analysis that determines
all the necessary stimulus and internal logic states to ensure a complete, accurate and highly efficient characterization of that cell. Liberate supports complex cells including those required for low power design such as state retention flip-flops, level shifters, power switches and MTCMOS cells with sleep modes.