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Mentor Graphics inFact intelligent testbench automation solution is the first to use a graph-based approach to accelerate functional coverage closure and find design bugs early in the verification process.
With inFact, users can comprehensively describe the scenarios in which a device is expected to operate and apply intelligent algorithms to generate high-quality test sequences, monitor results, and ensure generation of non-redundant sequences when appropriate. inFact generates more unique verification cycles in a shorter amount of time and accelerates functional coverage by more than an order of magnitude over traditional constrained-random testbenches.
*Intelligent testbench technology automatically creates test sequences, data, and checks on-the-fly
*Advanced stimulus generation creates any combination of constrained random, non-redundant random, systematic, and directed test sequences
*Accelerates functional coverage closure for module, subsystem, and system-level verification
*Supports testbenches written in all standard high-level verification languages, such as SystemVerilog, SystemC, and C++
*Supports standard verification methodologies (OVM, AVM, VMM) and transaction-level environments