Enhanced Variable Rate Codec (EVRC-A) was standardized as IS-127 in 1995. The EVRC codec operates on each 20ms frame of 16-bit speech signals sampled at 8 KHz and generates compressed bit-streams with bit-rates of 9.6 kbps (full-rate), 4.8 kbps (half-rate), or 1.2 kbps (one-eighth rate) respectively. It is based on Relaxed Code Excited Linear Prediction (RCELP) algorithm. The codec chooses the bitrate based on the analysis of the input speech and the current operating mode (either normal or one of the reduced rate modes). It includes an adaptive noise suppressor to handle background noise and is robust under frame erasures and channel errors. The codec was primarily developed for use in CDMA networks.
Salient features (of CouthIT implementation):
Based on IS-127/3GPP2 specification.
Optimized ASM/C implementation.
Operates on speech signals sampled at 8 KHz.
Support for 9.6 kbps, 4.8 kbps, and 1.2 kbps bitrates.
The maximum and minimum bitrates can be configured during initialization.
The noise suppression module can be configured during initialization.
Support for RTP payload format as specified in RFC 3558.
Supports integrated Packet Loss Concealment (PLC) algorithm.
Support for post-filter operation, configurable at frame boundary.
Support for DTMF and TTY/TDD signals as specified in the standard.
Supports integrated DTX mode of operation.
Optional support for xDM APIs.
Little- and big-endian implementation on ARM.
Scope of Testing:
Bit-exact with the standard test vectors
Module is fully interruptible.
ARM implementation tested for any illegal memory access.
Tested for compliance with register preservation requirements
Tested for Input buffer corruption
Tested for I/O buffer alignment requirements
Tested for multi-instance implementation
Tested for 100% code coverage
Range validation for all the API parameters
Tested for packet loss conditions with 5% loss to 25% loss
ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
For most current information on the performance specifications and availability of developed implementation on ARM cores, please send in your enquiry to firstname.lastname@example.org