ARM’s highest performing processor, extending the capabilities of mobile and enterprise computing. Read More...
Enhanced Variable Rate Codec – B (EVRC-B) was standardized by 3GPP2 in 2006. The EVRC codec operates on each 20ms frame of 16-bit speech signals sampled at 8 KHz and generates compressed bit-streams with bit-rates of 8.3, 7.57, 6.64, 6.18, 5.82, 5.45, 5.08, and 4.0 kbps (source encoding rates) respectively. EVRC-B is based on the Code Excited Linear Prediction (CELP), Prototype Pitch Period (PPP), and Noise Excited Linear Prediction (NELP) coding algorithms. It makes greater use of the intermediate coding rates through increased awareness of the nature of the individual speech samples. This more sophisticated coding approach allows EVRC-B to offer a voice quality equivalent to EVRC-A (IS-127), but at significantly lower average coding bit rates. The codec was primarily developed to replace the existing EVRC-A codec used in CDMA networks.
Salient features (of CouthIT implementation):
Based on 3GPP2 specification.
Optimized ASM/C implementation.
Operates on speech signals sampled at 8 KHz.
Support for selecting anchor operating mode or average rate mode during initialization time.
Support for 8.3, 7.57, 6.64, 6.18, 5.82, 5.45, 5.08, and 4.0 kbps source encoding bit-rates.
Supports integrated Packet Loss Concealment (PLC) algorithm.
Support for post-filter operation, configurable at frame boundary.
The maximum and minimum bit-rates can be configured during initialization.
The noise suppression module can be configured during initialization.
Support for dim and burst, eighth rate hangover, and null traffic frame features specified in the standard.
Support for RTP payload format as specified in RFC 4788.
Support for DTMF and TTY/TDD signals as specified in the standard.
Supports integrated DTX mode of operation.
Support for setting the minimum and maximum DTX update interval during initialization
Optional support for xDM APIs.
Little- and big-endian implementation on ARM.
Scope of Testing:
Bit-exact with the standard test vectors.
Module is fully interruptible.
ARM implementation tested for any illegal memory access.
Tested for compliance with register preservation requirements.
Tested for Input buffer corruption.
Tested for I/O buffer alignment requirements.
Tested for multi-instance implementation.
Tested for 100% code coverage.
Range validation for all the API parameters.
Tested with scratch contamination at frame boundaries.
Tested for packet loss conditions with 5% loss to 25% loss.
ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
For most current information on the performance specifications and availability of developed implementation on ARM cores, please send in your enquiry to firstname.lastname@example.org