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- First behavioral-level formal analysis tool for verilog and
- Describe interface protocols and design properties using
behavioral-level testbench with minimal random
constraints,reference models, and properties vs complex RT -
- Eliminate major development effort to write constraints
guiding coverage test generation for corner cases.
Support reference model based methodologies which greately
improve scalability of formal analysis.
- Tightly integrated simulation and formal engines provide
simulation-centric feel and better control over case analysis
- More efficient for both designers and verification engineers