Vista by Mentor Graphics Corporation
Consumer, mobile, networking and storage systems with multi-core processors are rapidly becoming more complex, making architecture decisions increasingly critical, and impacting the design's competitive advantage.
Vista™ Architect is a complete TLM 2.0-based solution for architecture design, analysis and verification enabling system architects and SoC designers to make viable architectural decisions. This is accomplished by prototyping and analyzing complex systems to ensure optimized architectures, shorter implementation time and first-pass success.
Vista Model Builder, a sub-set of the Vista Architect solution, facilitates TLM model creation with a new scalable modeling methodology, based on TLM 2.0, where communication, functionality, and timing/power attributes are independently modeled. This important modeling practice allows a single functional model to be maintained throughout the design cycle at various implementation phases and through alternative design options. Vista Model Builder automates modeling functionality with a TLM code skeleton that is automatically derived from a set of ports, registers and memory declarations, generating compact SystemC source code compliant with TLM 2.0.
Timing and power can be specified in a top-down manner through a set of powerful policies. This enables users to quickly change the timing policies for each micro-architecture model and test various configurations and pipeline strategies while keeping the functionality intact. Users can refine the timing and power accuracy from high-level approximation down to precise timing in a matter of minutes.
Vista TLM Models
Vista Architect offers a set of fast generic models for initial platform assembly and early validation. All models are TLM 2.0 compliant and can be used as building blocks for assembling any target platform. In addition, users can use ARM’s fully validated Fast Models for a range of ARM processors with Vista Architect.
During the architecture design phase, models can be instantiated and assembled into various architecture configurations, interconnect layering and memory hierarchies. Vista's powerful block diagram editor provides intuitive graphical platform assembly, editing and visualization.
Vista Architect offers one of the industry's most advanced SystemC debug toolsets designed to validate and debug SystemC TLM platforms, the correct interaction among various IPs and appropriate flow of data. Vista Architect also offers a powerful analysis and reporting toolset that allows users to intuitively analyze different performance and power metrics.
Users can test and debug the hardware driven by software or produce a virtual platform to run firmware, operating systems or hardware dependent software applications.
- Mobile Computing