The Cadence(R) Encounter(R) digital IC RTL-to-GDSII design platform directly supports ARM deliverables for both their soft and hard IP cores. For soft IP, the Encounter Digital Implementation (EDI) System’s RTL sythesis capabilities can directly read source HDL and synthesis scripts. For hard IP, including cores available through ARM's foundry program, the EDI System can read all the necessary abstract models provided by ARM. The Cadence Encounter Power System (next generation VoltageStorm) and the Cadence Encounter Timing System (including CeltIC technology) provide a complete and integrated signoff environment for timing, SI, and power analysis and are fully supported as standard deliverables for ARM’s foundry cores.
As an integrated RTL-to-GDSII design environment, the Encounter platform provides a complete flow—from RTL synthesis and test design through physical prototyping and partitioning to final timing and manufacturing closure. It offers highest quality of silicon (timing, area, and power with wires), accurate verification, SI-aware routing, and the latest yield and low power design capabilities that are critical for advanced 65nm designs.