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This course covers the Cortex-M1 ARM core targetting FPGA SoCs
This course is split into 3 important parts:
A tutorial has been developed by ACSYS to facilitate the understanding of Cortex-M1 low level programming, therefore labs can be replayed after the course.
The course explains how to design a SoC based on Cortex-M1, clarifying the operation of the interconnect and the debug facilities integrated in the CPU.
Labs can be run under 2 possible environments: Eclipse/RVDS or Keil IDE
For open courses, labs are run under Eclipse/RVDS.
A more detailed course description is available on request at firstname.lastname@example.org
Knowledge of ARM7/9.
This course does not include chapters on low level programming.
ACSYS offers a large set of tutorials to become familiar with RVDS, assembly level programming, compiler hints and tips.
More than 12 correct answers to Cortex-R prerequisites questionnaire.
ARM Cortex-M1 INTRODUCTION
ARM Cortex-M1 CORE
OVERVIEW OF THUMB-2 INSTRUCTION SET
AMBA3.0 INTERCONNECT SPECIFICATION
AHB - ADVANCED HIGH PERFORMANCE BUS
APB - ADVANCED PERIPHERAL BUS
AHB CORTEX-M1 PORTS