• Electrically Programmable PLL for multiple applications
• Wide Ranges of Input and Output Frequency for diverse clocking needs
• Implemented with Analog Bits’ proprietary architecture
• Fully integrated inside industry standard or other customized IO ring
• Occupies zero core area
• Low power consumption
• Spread Spectrum tracking capability
• Requires no additional on-chip components or band-gaps, minimizing power consumption
• Excellent jitter performance with optimized noise rejection
Analog Bits’ Low Power Wide Range PLL addresses markets and applications that demand very low power and optimized for area efficiencies. In addition, consumer devices have restrictions on supply voltage due to battery restrictions or board restrictions. The PLLs are designed for standard digital logic processes and implement robust design techniques to work in noisy SoC environments. The PLLs can address a large portfolio of applications, ranging from non-integer clock multiplication to programmable clock synthesis for multi-clock generation.
The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and EGPFET/EGNFET 1.8V medium-oxide IO devices. The PLL resides inside the IO ring including two analog power supply pads, occupying no core area. In order to minimize noise coupling and maximize ease of use, the PLL incorporates a proprietary ESD structure, which is proven in several generations of processes. Eliminating band-gaps and integrating all on-chip components such as capacitors and ESD structures, helps the jitter performance significantly and reduces stand-by power. The PLL macro fits into any standard IO pad pitch and is available for both staggered and in-line IOs.