Tessent® MemoryBIST provides a complete solution for at-speed testing, diagnosis, repair, debug, and characterization of ARM embedded memories.
Tessent MemoryBIST includes a unique comprehensive automation flow that provides design rule checking, test planning, integration, and verification all at the RTL or gate level. The back-end flow for memory test (debug and characterization) is managed by Tessent SiliconInsight® Memory, an interactive, desktop-based debug environment.
Tessent MemoryBIST fully supports the ARM shared bus interface to the memories internal to the processor core IP. This interface provides an integrated BIST solution for the Processor core which allows full test access to all memories embedded within each processor core and does not interfere with the shared bus performance.
Tessent BIST models are generated by ARM memory compilers for advanced processes.
- Supports the ARM shared bus Interface
- Test algorithms may be defined during design, or post silicon during test
- Automated diagnosis and repair
- Supports any number of power domains