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Higher quality verification with less effort
Today's designs rely heavily on a variety of industry standard interfaces. To effectively verify these designs, designers often spend valuable time building and verifying verification components or VIP related to these standards. Using Questa® Verification IP you can reduce the overall testbench development time and complete more verification with less effort. Your engineers are freed from spending time on standard functionality giving them more time to focus on differentiating features.
The verification components in the Questa Verification IP library fit any verification environment. By facilitating and enhancing the application of transaction-level modeling (TLM), advanced SystemVerilog testbench features (such as constrained random testing), modern verification methodologies (such as OVM and UVM), and seamlessly integrating with other Mentor tools (such as Questa Verification Management, Questa Questa inFact and Veloce), Questa Verification IP increases productivity even further.
Questa Verification IP delivers a common interface across the library of protocols. This results in a scalable verification solution for popular protocols and standard interfaces, including stimulus generation, reference checking, and coverage measurements that can be used for RTL, TLM, and system-level verification.
Verification with Questa Verification IP is straight forward: simply instantiate it as a component in your testbench. The built-in capabilities of Questa Verification IP automatically provides the entries for the coverage database so you have the metrics in place to track whether all necessary scenarios are covered.
Questa Verification IP is also integrated with the Questa debug environment and makes use of the transaction viewing capability in Questa so that you can get both signal-level and transaction-level debugging capabilities.
• Stimulus generation
• Protocol checking
• Test suite, compliance tests
• Coverage collectors
• Transaction level debug
• Native OVM and UVM support
• Reduces testbench development time
• Supports both RTL and TLM abstraction levels
• Includes support for verification planning
• Fits in any verification environment, including OVM and UVM
• Increases quality and productivity
• AMBA (AHB, APB, AXI, AXI4, APB3 and AXI-LP)
• Ethernet (10/100, 1G, 10G, 40G, 100G)
• SPI 4.2
• USB 2.0, OTG & 3.0
• PCIe 1.1, 2.0 and 3.0
• DDR2, DDR3
• OCP 2.2 (including 3.0 writersp_enable and OCP disconnect)
ARM Protocols Supported
• AMBA (AHB, APB, AXI, APB3 and AXI-LP, AXI4, ACE)