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Transforms Design Analysis, CDC Checking, SDC Creation and Validation
The Blue Pearl Software Suite is the next generation EDA (electronic design automation) solution to automate RTL analysis, CDC (clock domain crossing) checking, SDC (Synopsys Design Constraints) creation and validation.
The Blue Pearl Software Suite augments existing EDA tool flows with a native Windows or Linux user experience. It gives users immediate feedback on design analysis and CDC checking, incorporating new visualization techniques for validating automatically-generated timing constraints.
Blue Pearl Suite minimizes design revisions
Automatically checks HDL for compliance with user-selected properties, including linting, DFT, FSM, coding style, clock generation and gating, initialization, and more.
Clock Domain Crossing Checks
Finds both unsynchronized and synchronized clock domain crossings, including single-bit and data bus, user-specified synchronization schemes, FIFOs, and data reconvergence.
Timing Constraint Generation and Management
Reads RTL and statically identifies complex false and multi-cycle paths, including those due to complex control logic.
Identify Longest Paths
Finds longest RTL paths from port-to-port, DFF-to-DFF, DFF-to-port, and port-to-DFF.
The Blue Pearl Software Suite addresses the needs of FPGA, ASIC, and COT designers by offering support for Verilog, SystemVerilog and VHDL in both Windows and Linux environments using either a GUI or command line interface. Output messages can be quickly filtered and viewed using the intelligent message management in the GUI, where waivers can be set and tracked, or directly from the SQL database without using the GUI.
Ease of Use
The Blue Pearl Software Suite allows users the flexibility to personalize the environment and verify results visually. Design set up is easy and flexible, offering a new user experience for EDA engineers. New and experienced designers can rapidly view timing constraints and SQL-format design analysis results from multiple runs.
Generate SDC Files
The Blue Pearl Software Suite can identify functional false and mult-cycle paths and automatically generate constraints for them. These constraints can be written into SDC files compatible with various synthesis tools, along with place-holder clock and I/O constraints. Audit trails and assertions in PSL or SVA are automatically generated for each false path. These assertions can be taken into simulation to check for firing, or imported into a formal property checker.
Other available capabilities allow you to migrate SDC constraints up or down your design hierarchy, and to visually compare constraints between different SDC files.
Visual Verification Environment™
The Blue Pearl Software Suite includes a unique Visual Verification Environment that enables users to perform a differential analysis on different design revisions and easily view automatically-generated timing constraints, SDC assertions, and schematics of timing exception paths.
As a result, the user can quickly understand the reasons why specific paths are false and can easily validate the accuracy of the timing constraint visually.