ARM’s highest performing processor, extending the capabilities of mobile and enterprise computing. Read More...
A state-of-the-art design flow engine that seamlessly integrates all aspects of RTL to GDSII execution seamlessly leveraging state of the art 3rd party EDA tools in various phases of the design including database management, compute and license utilization & design flow management.
By utilizing ACT and leveraging years of experience in working on ARM processor embedded SOC designs, SoCtronics engineers are able to reduce RTL to GDS convergence time while maintaining consistent first-time-correct-silicon track record. ACT flow can be used to optimize performance and/or power on the entire embedded design or only the processor or only outside the processors as in the case of hard macro embedded SOC chip designs.
A state of the art low power flow to take your design beyond what standard EDA tools provide. Seamlessly integrated into ACT (or can be run standalone) it enables complex designs with power islands, integrated (coarse and fine grain) power gating, multi-voltage designs, automated power grid generation and low power verification.
Leverages "G" and "HP" type technology variants for superior performance for CPU, GPU, Networking requirements. Tailored design flows with in house utilities for timing performance optimization. Leverages Multi-Vt device option for quick timing fixes.
Leverages "LP", "HPL" type technology variants for leakage reduction. In house experts can provide power performance analysis to decide the right technology node and transistor mix options. In house SmartPower flow enabled for micro-architecture to device level optimizations enabling power gating, multi-Vcc domains, multi-Vt and CD Bias options.