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Mentor Graphics Questa® inFact is the industry’s most advanced testbench automation solution. It targets as much functionality as traditional constrained random testing, but achieves coverage goals 10X to 100X faster.
This enables engineering teams to complete their functional verification process in less time, and/or to expand their coverage goals, testing functionality that previously fell below the cut line. Questa inFact also generates tests that an engineer might not envision, reaching difficult corner cases that alternative testing techniques typically miss. Using Questa inFact ensures high quality products.
Revolutionary results are not enough. Advanced technology must fit into existing processes and flows. Questa inFact can be integrated into current verification environments with little to no disruption. It supports UVM (and OVM) methodologies; standard languages such as SystemVerilog, SystemC, C/C++; and even other proprietary testbench languages. And if you are looking for an incremental way to move from a proprietary language to SystemVerilog, Questa inFact can provide a natural bridge, offering the benefits of a standard language while supporting legacy verification IP written in a non-standard language.
The number of companies turning to Questa inFact is growing exponentially. The minimum result experienced to date has been 10X faster achievement of target coverage. But many companies have gained 100X or better. Why such dramatic gains in productivity? The nature of constrained random testing lends itself to uncontrollable redundancy. While some repetition can be valuable, Questa inFact enables engineers to control the amount of redundancy desired, while generating the same or a higher quantity of tests.
• Intelligent testbench technology automatically creates test sequences, data, and checks on-the-fly
• Advanced stimulus generation creates any combination of constrained random, non-reduncant random, systematic and directed test sequences
• Accellerates functional coverage closure for module, subsystem and system level verification
• Verification scenarios are compactly described by rules and compiled into graphs, significantly reducing testbench development efforts
• Testbenches can achieve different verification goals as determined by the user
• Supports testbenches written in all standard high level verification languages such as SystemVerilog, SystemC and C++
• Supports standard verification methodologies (UVM, OVM, VMM, AVM) and transaction-level environments