ARM’s highest performing processor, extending the capabilities of mobile and enterprise computing. Read More...
The CLP-30: High Throughput Pipelined IPsec Engine is a highly integrated, silicon-proven security engine that features an enhanced architecture aimed at achieving high-performance IPsec packet processing ranging from 200 Mbps to 20 Gbps (with small packet traffic).
The design increases bandwidth and throughput compared to the CLP-25: Configurable IPsec (ESP/AH) Engine by implementing separate inbound and outbound packet processing engines, offering cipher and hash options and the ability to support multiple packets in flight. The CLP-30 supports an SoC bus master interface for DMA transfer of packet and security association data to and from memory and a slave interface for command and status information. SoC designers find the concept of protocol-aware cryptographic offload as the right architectural approach as it offers a flexible and scalable approach unlike the high gate count, hard-wired, in-line engines currently available on the market.
The High Throughput Pipelined IPsec Core also integrates seamlessly in ARM-based SOCs and enables designers to efficiently balance: power, performance, and silicon area.