PE-CRDMA is a DMA (AHB/AXI) engine with crypto blocks to off-load crypto engine processing.The engine is used in conjunction with a protocol processor to realize CRDMA, MACSEC protocols. The IP is flexible to route data between the crypto and authentication blocks for efficient data throughput.
PE-CRDMA provides a DMA type of interface for programming pointers to the security association data, packet pointers. The DMA performs scatter/gather data fetching and security association data along with the keys. The state machine schedules the crypto engines based on the protocol selection and packet boundaries. The hardware engines perform the encryption and authentication in sequence or in parallel.
PE-CRDMA transfers the data back to the host memory after the crypto processing. The authentication data and Key Out
data will be written to buffer specific location (bd specified pointer). In addition the performance of the Security Engines
can be traded with the design size.
The PE-CRDMA is suited to realize security a variety of security blocks like
1.Independent block to perform Crypto Processing
2.Can be easily integrated into an existing data path
3.Packet interface and Key interface is programmable
4.Multiple flavors of design for different performancerequirements (different pipeline stages).
1.Encryption/Authentication runs in parallel or in succession..
2.Suitable for ESP or AH protocol.
3.Encryption Engines : AES ,TDES,RC4,Kasumi,SNOW 3G.
4.Authentication Engines :SHA-1, SHA-256, MD-5,AES-GCM,AES-CBC,AES-xCBC,HMAC.
5.Bus Interface AXI,AHB.
6Performance upto 200MHz in 90nm.
7.AES Core engine runs up to 3.2 Gbps in 90 nm @ 300 MHz.
8.Optional RAM to counter BUS latencies..
9.Works with PE-True Random Number, Psuedo Random Number and Public Key Cryptography Engines.
10.Inbound and Outbound FIFO (SRAM).
1Fully Synthesizable RTL .
2.Testbenches and Testcases.
3.ASIC Synthesis Scripts..
4.FPGA Synthesis Scripts.