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*****
University DesignStart Programask ARM
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University Program - Overview

The University Program provides and encourages the use of ARM technology as teaching aids in universities and other higher education establishments.

University courses which focus on System-on-Chip design, computer architecture, embedded systems development or general programming can benefit from using ARM processors and development systems.

The program will enable university lecturers/academics to gain access to a set of teaching resources to allow courses to be developed around the ARM architecture from both the hardware, software and systems aspects.

University DesignStart Program

Academic establishments can gain access to processor simulation environments for ARM technology and can develop courses based around the latest processors used in electronic industry today. These simulation environments are based on real foundry processes available in the current marketplace.

Academic establishments wishing to participate in the University DesignStart Program need to register with ARM. Once registered, qualified individuals may download DesignStart Kits for the ARM processor directly from the ARM web site.

Two popular ARM processors are available in this program

University DesignStart Program Processor Characteristics

 Processor

Area
mm2

 Power Consumption
mW/MHz

 Frequency
(Worst Case)

 Cache Size

 0.18µm

 

 

 

 

 ARM7TDMI

 0.5 

          0.25 

       84 

       - 

 ARM926EJ

 8.98

          1.82 

     200 

  16K/16K


0.13µm

 

 

 

 

ARM7TDMI

 0.3

          0.06

    125

        -

ARM926EJ

 2.4

          0.5

    238

   8K/8K

ARM926EJ

 5.1

          0.44

    243

  16K/16K

 

 

         

   

 

For a full schedule of University DesignStart processor implementations, click here.

To register for the DesignStart program click here.

The University DesignStart Kit is comprised of the following deliverables:

  • Documentation including User Guide and Integration Manual
  • Design Simulation Model allowing RTL level simulation
  • Foundry process specific timing view (.lib and .CLF format)
  • Foundry process specific abstract layout view (.LEF and .FRAM format)
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