ARM11 MPCore

The ARM11TM MPCoreTM synthesizable processor implements the ARM11 microarchitecture and can be configured to contain between one and four processors delivering up to an aggregate 2600 Dhrystone MIPS of performance. Providing a scalable solution, the ARM11 MPCore processor provides existing software portability across single CPU and multi-CPU designs. The ARM11 MPCore processor provides enhanced memory throughput of 1.3Gbytes/sec from a single CPU, and a solution that delivers greater performance at lower frequencies than comparable single processor designs, offering significant cost savings to system designers, while maintaining full compatibility with existing EDA tools and flows.  The ARM11 MPCore processor also simplifies otherwise complex multiprocessor design, reducing time-to-market and total design cost.
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The ARM11 MPCore processor supports a fully coherent data cache, providing the designer with a unique level of flexibility across various symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP), or any combination of either style of multiprocessor design.  The MPCore processor increases a solution's performance via the ability to cache shared data, increases system responsiveness by allowing workloads to be balanced between processors with the portability of existing multitasked applications, and enabling scalability through efficient processor utilization for multithreaded applications, typical of the workloads of today's rich consumer devices.

The ARM11 MPCore processor provides the manufacturer flexibility to use the same core with different configurations for a range of products having various design requirements. The MPCore processor's consistent bus interfaces and scalable design also enables the performance and power advantages of a multiple processor design while also reducing the total costs and risks of delivering next generation digital devices.

The ARM11 MPCore processor supports the ARMv6 architecture, with SIMD media extensions for next-generation rich multimedia and convergent devices and ARM Jazelle® Java acceleration.  It also features configurable level 1 caches, 64-bit AMBA AXI^TM interfaces, Vector Floating Point coprocessors and programmable interrupt control and distribution. The processor supports Adaptive Shutdown of unused processors to give dynamic power consumption as low as 0.49 mW/MHz from a generic 130nm process excluding cache. ARM Intelligent Energy Manager (IEM) can further reduce consumption to as low as 0.30mW/MHz by dynamically predicting the required performance and lowering the required voltage and frequency. The ARM11 MPCore enables SoC designers to view the core as a single “uniprocessor”, simplifying SoC development and reducing time-to-market.

Features

• Highly configurable
  • Flexibility of total available performance from implementations using between 1 and 4 processors.
  • Sizing of both data and instruction cache between 16K and 64K bytes across each processor.
  • Either dual or single 64-bit AMBA 3 AXI system bus connection allowing rapid and flexibility during SoC design
  • Optional integrated vector floating point (VFP) unit
  • Sizing on the number of hardware interrupts up to a total of 255 independent sources
    
• Efficient processing
  • Rich ARMv6K architecture-based multiprocessor-capable instruction set architecture providing architectural enhancements that further improve performance of a multiprocessor capable OS
  • Support for ARM Thumb ^® instruction set
  • ARM Jazelle technology
  • ARM DSP extensions
  • SIMD (single instruction, multiple data) media processing extensions delivering up to 2x performance for video processing
    
• Advanced energy management features
  • Designed for low power by providing gate level shutdown of unused resources
  • Supporting the ability for each processor to go into standby, dormant or power off energy management states providing control over both the dynamic and static energy consumed by the processor and memories with savings of up to 85%
  • Support for dynamic voltage and frequency scaling using technology such as ARM Intelligent Energy Manager (IEM)
    

• High performance memory system
  • 16-64k independent data and instruction cache per processor with support for full data coherence.
  • Ability for data to move between each processor’s cache permitting rapid data sharing without accesses to main memory.
  • Optimized L1 memory system significantly increasing throughput and further lowering power consumption.
  • Fully physical index, physically tagged data cache removing the performance costs from de-aliasing addresses on larger caches or needing to flush caches on an OS context-switch
  • Data cache allocation on both read and writes along with an intelligent merging write buffer with forwarding to greatly reduce main memory accesses and significantly increase the ability to form bursts from multiple memory requests.
  • Unique 'cork-screw' cache memory design accelerating cache allocation and eviction to a single cycle
    
• Simple design integration
  • ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models.
  • Integration of the essential system components provides a standard OS view of the key functionality and reduces the complexity and risk associated in gaining OS support.
  • Utilizes 64-bit AMBA 3 AXI bus interconnect simplifying system interconnect while providing higher data bandwidth and easier timing closure
    
• Software support environment
  • Standard ARM programming model with support for existing OS, middleware and applications
  • Availability of Linux 2.6 SMP capable operating system and tools. Click to download. 
  • Support for both asymmetric multiprocessor (AMP) workloads, and for symmetric multiprocessing (SMP) multiprocessor programming paradigms

Core area, frequency range and power consumption are dependent on process, libraries and optimizations. The numbers quoted above are illustrative of synthesized cores using general purpose TSMC process technologies and ARM Artisan standard cell libraries and RAMs.

The speed optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density. All figures include internal peripherals and interrupt system.

The cache sizes are specified as InstructionCache/DataCache. The area w/o cache numbers quoted exclude RAM area, but include all logic including memory management, cache control and debug. The area with cache numbers quoted includes the core, the specified instruction and data caches and all necessary RAMs.

* Worst case conditions –  90nm process - 0.9V, 125C, slow silicon
† Typical case conditions – 90nm process - 1V, 25C, typical silicon