ARM7EJ-S

Applications:

• Personal audio (MP3, WMA, AAC players)
• Java enabled wireless handset
• Pager
• Ink-jet/bubble-jet printer
• Digital still camera
• PDA

Features:

• 32/16-bit RISC architecture (ARM v5TEJ)
• ARM 32-bit instruction set for maximum performance and flexibility
• Thumb 16-bit instruction set for increased code density
• Java byte-code execution unit
• Unified 32-bit data bus carries both instructions and data
• Five-stage pipeline for increased performance
• 32-bit ALU and high-performance multiplier
• DSP instruction set
• Very small die size and power consumption
• Coprocessor interface
• Extensive debug facilities:
  – EmbeddedICE-RT real-time debug unit
  – JTAG interface unit
  – Interface for direct connection to Embedded Trace Macrocell (ETM)

Benefits:

• Synthesizable design can be ported to many process technologies and optimized for speed or size
• Unified memory bus simplifies SoC integration process
• ARM and Thumb instructions sets can be mixed with minimal overhead to support application requirements for speed and code density
• Java-execution mode allows existing software to be reused whilst adding accelerated support Java applications
• DSP instructions support real-time operations removing the need for costly DSP processors
• Small die size reduces overall SoC area, cost and power consumption
• Static design and lower power consumption are essential for battery-powered devices
• Scannable design means high levels of testability can be achieved
• Instruction set can be extended for specific requirements using coprocessors
• EmbeddedICE-RT and optional ETM units enable extensive, real-time debug facilities
• ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models.

Core area, frequency range and power consumption are dependent on process, libraries and optimizations. The numbers quoted above are illustrative of synthesized cores using general purpose TSMC process technologies and ARM Artisan standard cell libraries and RAMs.

The speed optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density.

* Worst case conditions –   0.18µm process - 1.62V, 125C, slow silicon ;  0.13µm process - 1.08V, 125C, slow silicon ;  90nm process - 0.9V, 125C, slow silicon
† Typical case conditions– 0.18µm process–1.8V, 25C, typical silicon ;  0.13µm process - 1.2V, 25C, typical silicon ; 90nm process - 1V, 25C, typical silicon