ARM Cortex-M3The Cortex-M3 processor, based on the ARMv7-M architecture, has a hierarchical structure. It integrates the central processor core, called the CM3Core, with advanced system peripherals to enable integrated capabilities like interrupt control, memory protection and system debug and trace. These peripherals are highly configurable to allow the Cortex-M3 processor to address a wide range of applications and be more closely aligned with the system requirements. The CM3Core and the integrated components have been specifically designed to meet the requirements of minimal memory implementation, reduced pin count and low power consumption. 
The central CM3Core is based on the Harvard architecture characterized by separate buses for instructions and data. The processor differs from the von Neumann architecture based ARM7 family of processors which use the same signal buses and memory for both instructions and data. By being able to read both an instruction and data from memory at the same time, the Cortex-M3 processor can perform many operations in parallel, speeding application execution. The core pipeline has 3 stages: Instruction Fetch, Instruction Decode and Instruction Execute. When a branch instruction is encountered, the decode stage also includes a speculative instruction fetch that could lead to faster execution. The processor fetches the branch destination instruction during the decode stage itself. Later, during the execute stage, the branch is resolved and it is known which instruction is to be executed next. If the branch is not to be taken, the next sequential instruction is already available. If the branch is to be taken, the branch instruction is made available at the same time as the decision is made, restricting idle time to just one cycle. The CM3Core contains a decoder for traditional Thumb and new Thumb-2 instructions, an advanced ALU with support for hardware multiply and divide, control logic, and interfaces to the other components of the processor. The Cortex-M3 is a 32-bit processor, with a 32-bit wide data path, register bank and memory interface. There are 13 general-purpose registers, two stack pointers, a link register, a program counter and a number of special registers including a program status register. The Cortex-M3 processor supports two operating modes, Thread and Handler and two levels of access for the code, privileged and unprivileged, enabling the implementation of complex and open systems without sacrificing the security of the application. Unprivileged code execution limits or excludes access to some resources like certain instructions and specific memory locations. The Thread mode is the typical operating mode and supports both privileged and unprivileged code. The Handler mode is entered when an exception occurs and all code is privileged during this mode. In addition, all operation is categorized under two operating states, Thumb for normal execution and Debug for debug activities. The Cortex-M3 processor is a memory mapped system with a simple, fixed memory map for up to 4 gigabytes of addressable memory space with predefined, dedicated addresses for code (code space), SRAM(memory space), external memories/devices and internal/external peripherals. There is also a special region to provide for vendor specific addressability. The Cortex-M3 processor enables direct access to single bits of data in simple systems by implementing a technique called bit-banding. The memory map includes two 1MB bit-band regions in the SRAM and peripheral space that map on to 32MB of alias regions. Load/store operations on an address in the alias region directly get translated to an operation on the bit aliased by that address. Writing to an address in the alias region with the least-significant bit set writes a 1 to the bit-band bit and writing with the least-significant bit cleared writes a 0 to the bit. Reading the aliased address directly returns the value in the appropriate bit-band bit. Additionally, this operation is atomic and cannot be interrupted by other bus activities. Traditional ARM7 based systems support only aligned data access, allowing data to be stored and accessed only along aligned word boundaries. The Cortex-M3 processor implements unaligned data access that enables unaligned data transfers in a single core access. When unaligned transfers are used, they are converted into multiple aligned transfers and remain transparent to application programmers.
In addition the Cortex-M3 processor supports 32-bit multiply operations in a single cycle and also supports signed and unsigned divide operations with the SDIV and UDIV instructions that take between 2 and 12 cycles depending upon the size of the operands. The division operation is completed faster if the dividend and the divisor are closer in size. These improvements in the mathematical capabilities make the Cortex-M3 ideal for many numerically intensive applications such as sensor reading and scaling or hardware-in-the-loop simulation systems.
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