SecurCore SC100

• Smart Cards
• SIM
• Banking
• Medical
• Pay TV

Features:

• Fully synthesizable design
• Randomized processor layout based on customer design specifications
• Advanced, secure debugging and test methodology
• One-way development process to ensure security during development
• Controlled access to design stages via flexible software and emulation solutions
• Memory Protection Unit performs memory management type functions securely
• Specific counter-measures to help prevent analysis of current flows
• Energy and space-saving features, including ARM Thumb technology for code compression
• Rapid ASIC or ASSP integration with reduced time-to-market

Benefits:

• Application of 32-bit processing through a compact synthesizable processor
• Reduced development costs
• Shorter development cycle time
• Single development toolkit
• 4GB non-segmented memory architecture for simplified software development
• Higher system performance
• Multiple sourcing from industry-leading silicon vendors
• Excellent debug support for SoC designers
   

Core area, frequency range and power consumption are dependent on process, libraries and optimizations. The numbers quoted above are illustrative of synthesized cores using general purpose TSMC process technologies and ARM Artisan standard cell libraries and RAMs.

The speed optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density.

* Worst case conditions –   0.18µm process - 1.62V, 125C, slow silicon ;  0.13µm process - 1.08V, 125C, slow silicon
† Typical case conditions– 0.18µm process–1.8V, 25C, typical silicon ;  0.13µm process - 1.2V, 25C, typical silicon