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Power Management Kit

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The ARM® Power Management Kit (PMK) can drastically reduce the dynamic and leakage power of a chip. Included is a variety of components to implement a number of power management techniques, seamlessly integrated in the latest low power design flows by the leading EDA vendors.

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To build successful multimillion gate SoC designs, dynamic and leakage power savings are essential for all designs to enable longer battery life or reduce system cost. 

PMK dynamic and leakage power reduction are proven in silicon on ARM Physical IP test silicon as well as on ARM processor designs.

  • Dynamic power can be reduced by lowering the operation voltage for the entire chip or blocks; different on-chip voltage islands require the use of level shifters

  • Leakage power can be dramatically reduced by powering down blocks of the chips, this is can be achieved by on-chip power gates by switching power (VDD) or ground (VSS)

  • If powering down parts of the chip, it may be necessary to maintain the state of sequential elements: this is supported via retention flip-flops, retention scan flip-flops and retention latches

Leakage Power Explosion

 


PMK components can be used for all types of designs
    
from low frequency controller applications in MHz range ... 
    
... to high performance GHz applications  
  • Leakage savings of up to 99% in sleep modes

  • Fast wake-up time from sleep mode in hundreds of ns

  • No special well spacing required within blocks
    • Allows for smallest area for power gates
    • No placement requirements for power gates and level shifters
    • Eases implementation
       
  • No performance penalty between regular and retention flip-flops

  • Wide shifting range for up level shifters; special circuitry ensures complete voltage shift

  • Down shifters have no special circuitry; size and performance match AND/NAND gates


Very large cell set to ensure optimal implementation of all types of designs.
   -  
About 250 cells per Vt or channel length at 32/45nm 
   - 
Smaller cell set in more mature technologies
  • Functions
    • Power gate header cells to switch power (VDD) and footer cells to switch ground (VSS)
    • Up, down and bidirectional level shifters with and without isolation capabilities
    • Dedicated isolation cells
    • Retention flip-flops, retention scan flip-flops and retention latches
    • Supporting cells like always-on buffers and inverters
       
  • All functions are implemented in multiple drive strengths 
     
  • Includes UPF and CPF constructs, power aware back-end verilog models, well modeling
     
  • Patents granted on some design styles

  • Multi-Vt and channel length optimization for power gates and retention flip-flops for further leakage reduction

  • Multi-Vdd characterization and overdrive voltage support

ARM Power Management Kit Logic IP is used in conjunction with compatible ARM Standard Cell Libraries and may be used in complex SoC designs that require many types of IP across the design. In addition to Power Management Kit IP, ARM offers a wide variety of compatible Processor to Pads IP including ARM Processor, Multimedia, System and Physical IP, with which to develop your SoC.



Visit DesignStart to find ARM IP solutions for your SoC and start designing today.

ARM Physical IP ARM Processor IP ARM System IP ARM Multimedia IP
Standard Cell Libraries Cortex-A9

Memory Controllers

Mali-400
ECO Kits Cortex-A5

System Controllers

Mali-200
Embedded Memory Cortex-R4

Debug & Trace IP

Mali-VE6
Interface Cortex-M3 Peripherals Mali-VE3


You can view ARM Power Management Kits and other Physical IP products in DesignStart. Registered users of DesignStart can download Front-End Packages for all products that enable a comprehensive IP evaluation including place and route. DesignStart also includes access to technical documentation, including Datasheets and Application Notes.

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