The ARM® product family of Artisan® Physical IP solutions provide the building blocks to create highly optimized System-on-Chip (SoC) designs, reduce time to market and offer design choice without compromising silicon area and performance. With thousands of registered users and hundreds of designers per month downloading ARM Physical IP, ARM's proven track record ensures high-quality, re-usable IP to enable SoC design success. The products are offered in three platform solutions; AdvantageTM platform for performance, MetroTM platform for high density (small area) and Velocity high-speed PHYs . Within these platforms, ARM offers a wide range of high-performance and high-density, digital and analog products, for the manufacture of advanced SoCs. From the introduction of its Artisan memories and SAGE-XTM standard cell libraries, through its Artisan Free Library Program established in 1988, ARM continues to provide the most complete foundry and process support in the industry.
This support was enhanced in 2006 with the provision of Silicon on Insulator (SOI) support following the acquisition of SOISIC. SOI technology is a leading candidate to address the power and performance scaling issues faced by traditional bulk CMOS processes as they migrate to ever-smaller geometries. ARM develops standard cell libraries, embedded SRAM memory compilers and I/Os in SOI technologies, enabling the benefits of SOI to expand beyond full custom-designed ICs into the mainstream SoC market. ARM’s expertise derives from detailed understanding of the unique benefits of SOI process technology and the application of this technology to products it has developed from 250nm down to 65nm. With the scale of the ARM platforms and program offering, designers have the flexibility to optimize their designs. An example of this flexibility is the ability to implement critical speed parts from the Advantage-HS platform without compromising cost by implementing the high-density Metro platform for less performance critical parts of a SoC. The ARM Metro and Advantage platforms provide: Standard Cell Libraries
- Optimal SoC integration and improved time-to-market
- Comprehensive portfolio of standard cell libraries covering a wide spectrum of applications from high-density and low power to highest performance
- Advantage and SAGE-X for performance, power and area balanced application
- Metro libraries for high-density, low power requirement
- Advantage-HS and SAGE-HS for high performance design
- ARM Power Management Kit to actively reduce dynamic and leakage power
Memory Compilers - Small and fast repairable memory solutions
- Single- and dual-port SRAMs with optional Flex-Repair™ Redundancy
- Single- and two-port register files
- Diffusion and via programmable ROMs
- Speed, area and power optimized architectures
General Purpose I/Os - Full set of I/Os for pad ring construction and compatibility with other interface standards
- Wide variety of input level support; LVCMOS, LVTTL, CMOS
- Wide variety of drive strengths; 2, 4, 8, 16, 24 mA
- Three slew rate control levels on output drivers
- Robust ESD protection and latch-up immunity
- Staggered (pad limited) in line (core limited) and flip-chip configurations
Specialty I/Os - Industry standard compliant I/Os include:
- LVDS, SSTL, HSTL, PCI/X(Mode 1 & 2), PCI
- In-line(core-limited), staggered(pad-limited) and flip-chip bonding support
- Bus interface I/O designs address signal integrity, and noise isolation/generation
- Advanced features include: power management, data integrity, calibration, and pre-emphasis
Analog Timing IP Deskew PLL (Phase Locked-Loop) Deskew DLL (Delay Locked-Loop) CDR (Clock and Data Recovery PLL) Multiplier (M/N) clock synthesizer PLLs
The ARM Velocity platform consists of: Serial PHYs - Superior jitter performance, low power and small area, thus reducing system cost
- PHY for PCI-Express® Gen1 and Gen2
- XAUI/1-3.2Gbps Backplane PHY
- CEI-6 (SR) and XAUI/1-6.4Gbps backplane PHY
- Serial ATA 1&2 PHY
DDR PHYs - Configurable placement for reduced area and low-package cost supporting DDR1, DDR2, GDDR3, MDDR standards
ARM Physical IP Product Downloads ARM provides a portfolio of its Artisan Physical IP products through web access, with over 3500 products available for download. All products have complete front-end views and .lef files available for performance and area evaluation. The download products: five memory compilers, two I/O products and one standard cell library, form the Design Platform upon which SoC teams can accomplish their designs. By providing a common interface of simulation and tapeout views that does not change for each foundry, ARM helps to enable manufacturing flexibility and reduce time to market through designer familiarity and high-quality proven IP. All ARM physical IP available for download has been designed using the same ARM Process-Perfect™ Design Methodology. 
Free – Foundry Sponsored
The ARM Free Library Program provides design teams with a wide selection of products optimized for leading foundries' processes at no charge. The products are high-quality IP which has been licensed from ARM by the specified foundry and made available for download from the ARM website. Fee based products
The ARM product family of Artisan Physical IP also has many specialty products that are licensed to design teams for a fee. These products include: high-speed PHY, analog timing IP, general-purpose and specialty I/O, memory compiler and standard cell library solutions that are optimized for specific processes and foundries to provide unique functionality, density, power and/or area performance points which are not available in the ARM Free Library Program. These products can be used on the same SoC as the Free Library Program products to enable superior SoC integration through use of speed-optimized products and density-optimized products in different areas All front end views can be downloaded from the website free-of-charge with the Evaluation Design Kits. | 
