ARM High Speed Interface hardened PHY macros provide full DFI 2.0 compliance resulting in maximum support for ARM DDR Controllers or 3rd party DDR Controllers.

High Speed Interface Features

• DFI compliant PHY
• Multiple DDR standards supported
• Seamless interoperability between IP
• Low noise, high signal integrity
• Robust ESD enabling full speed designs

High Speed Serial Interface Features

• Extremely low jitter
• Smallest size in the industry
• Very low power
• 1-16 lane configurations ready for instantiation
• Wire bond and flip chip configurations
• Extensive manufacturing test support
• Silicon characterized
• Easy to use
• Comprehensive documentation
• Excellent noise immunity and signal integrity
• Few external components required

High Speed Serial Interface Benefits

• High Speed Interface IP completes the Processor to Pads solutions for ARM Processors, GPU and Fabric IP ensuring best implementation and optimal performance
• Higher margins delivered thru smaller die area, lower power and high yields
• Time To Market advantage leveraging broadest EDA views, silicon proven technology and manufacturing flexibility
• Lowest risk solutions with more ARM physical IP designs in production than all 3rd party IP providers combined