The Cortex-A5 processor provides a high-value migration path for existing ARM926EJ-S™ and ARM1176JZ-S™ processor designs. It achieves better than ARM1176JZ-S performance, better power and energy efficiency than the ARM926EJ-S, and 100% Cortex-A compatibility.
These processors deliver high end features to power and cost sensitive applications, featuring:
The Cortex-A5 comes designed for applications that require virtual memory management for high-level operating systems within an extremely low power profile.
|Mobile||Entry-level Smartphones, Feature Phones, Mobile Payments, Audio|
|Home/Consumer||Digital TV, DVD|
|Embedded/Industrial||MPU, Smart Meters|
Industry leading energy efficiency means the Cortex-A5 gets more work done per unit of energy, which means longer battery life and less heat dissipation in mobile devices. The Cortex-A5 is the smallest Cortex-A processor.
The Cortex-A5 processor provides full instruction and feature compatibility with the higher performance Cortex-A8, Cortex-A9, and Cortex-A15 processors - all the way down to the operating system level. The Cortex-A5 processor also maintains backwards application compatibility with Classic ARM processors including the ARM926EJ-S, ARM1176JZ-S, and ARM7TDMI®.
|ARM Cortex-A5 Performance, Power, and Area|
|TSMC 40LP||TSMC 40G|
|Process Type/Nominal Voltage||low leakage, 1.1V||performance, 1.0V|
|Performance or Frequency Optimized||Frequency||Frequency|
|Frequency||530~600 MHz (all RVt)
700MHz + with LVt
|Area excluding RAMs/cache||0.27mm²||0.27mm²|
|Area with 16K/16K cache||0.53mm²||0.53mm²|
|Area with 16K/16K cache + NEON||0.68mm²||0.68mm²|
|Dynamic Power||0.12 mW/MHz||<0.08mW/MHz|
|Energy Efficiency||13 DMIPS/mW||>20 DMIPS/mW|
Core area, frequency range, and power consumption are heavily dependent on process, libraries and optimizations.
ARM High Performance SC12 logic library and performance RAMs
Frequency at Slow Silicon/Vdd-10% (1.0V)/125C
10% OCV and 50ps clock uncertainty
Power at Typical Silicon/Vdd (1.1V)/25C
All nominal Vt transistors
|Dhrystone Performance||1.57 DMIPS / MHz per core|
Single core version also available
|Memory Management||ARMv7 Memory Management Unit|
|Debug & Trace||CoreSight™ DK-A5|
|Cortex-A5 Key Features|
|Thumb-2 Technology||Delivers the peak performance of traditional ARM code while also providing up to a 30% reduction in memory required to store instructions|
|TrustZone® Technology||Ensures reliable implementation of security applications ranging from digital rights management to electronic payment. Broad support from technology and industry Partners.|
|NEON Media Processing Engine (MPE)||The optional Cortex-A5 NEON MPE provides both the performance and functionality of the Cortex-A5 Floating Point Unit plus an implementation of the ARM NEON Advanced SIMD instruction set for further acceleration of media and signal processing functions
The MPE extends the Cortex-A5 Floating Point Unit (FPU) an additional register set supporting a rich set of SIMD operations over 8, 16, and 32-bit integer and 32-bit Floating-Point data types.
|Floating Point Unit (FPU)||The optional Cortex-A5 FPU is an implementation of the ARM Vector Floating Point v4 architecture, with 16 double-precision registers (VFPv4-D16). The unit provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic (IEEE 754).
The FPU supports all data-processing instructions and data types in the VFPv4 architecture and fully supports single-precision and double-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions.
|Configurable L1 Caches||The power optimized L1 Instruction and Data Caches are individually configurable from 4-64K. Optimized instances of ARM SRAMs are available.|
|High Performance AXI Bus||The Cortex-A5 implements a 64-bit unified AXI bus that supports multiple outstanding transactions, and has over 3x the memory bandwidth of the ARM1176JZ-S.|
|Advanced Multicore Technologies|
|Snoop Control Unit (SCU)||The SCU is the central intelligence in the ARM multicore technology and is responsible for managing the interconnect, arbitration, communication, cache-2-cache and system memory transfers, cache coherence and other capabilities for all multicore technology enabled processors.
The Cortex-A5 MPCore processor also exposes these capabilities to other system accelerators and non-cached DMA driven mastering peripherals so as to increase the performance and reduce the system wide power consumption by sharing access to the processor's cache hierarchy. This system coherence also reduces the software complexity involved in otherwise maintaining software coherence within each OS driver.
|Accelerator Coherence Port (ACP)||This AMBA® 3 AXI™ compatible slave interface on the SCU provides an interconnect point for a range of system masters that - for overall system performance, power consumption or reasons of software simplification - are better interfaced directly with the Cortex-A5 MPCore processor.
The interface acts as a standard AMBA 3 AXI slave, and supports all standard read and write transactions without any additional coherence requirements placed on attached components. However, any read transactions to a coherent region of memory will interact with the SCU to test whether the required information is already stored within the processor L1 caches. If it is, it is returned directly to the requesting component.If it missed in the L1 cache, then there is also the opportunity to hit in L2 cache before finally forwarding to the main memory.
For write transactions to any coherent memory region, the SCU will enforce coherence before forwarding the write to the memory system. The transaction may also optionally allocate into the L2 cache hence removing the power and performance impact of writing directly through to the off chip memory.
|Generic Interrupt Controller (GIC)||Implementing the recently standardized and architected ARM interrupt controller, the GIC provides a rich and flexible approach to inter-processor communication and the routing and prioritisation of system interrupts. Supporting up to 224 independent interrupts under software control, each interrupt can be distributed across CPU, hardware, prioritized and routed between the operating system and TrustZone software management layer. This routing flexibility and the support for virtualization of interrupts into the operating system, provides one of the key features required to enhance the capabilities of a solution utilizing a paravirtualization manager.|
System IP components are essential for building complex system on chips and by utilizing System IP components developers can significantly reduce development and validation cycles, saving cost and reducing time to market.
|Description||AMBA Bus||System IP Components|
|Advanced AMBA 3 Interconnect IP||AXI||NIC-400, PL301|
|DMA Controller||AXI||DMA-330 , PL330|
|Level 2 Cache Controller||AXI||L2C-310 , PL310|
|Dynamic Memory Controller||AXI||DMC-340 , PL340|
|DDR2 Dynamic Memory Controller||AXI||DMC-342|
|Static Memory Controller||AXI||SMC-35x , PL35x|
|TrustZone Address Space Controller||AXI||PL380|
|CoreSight™ Design Kit||ATB||CDK-11|
|The Mali™ family of products combine to provide the complete graphics stack for all embedded graphics needs, enabling device manufacturers and content developers to deliver the highest quality, cutting edge graphics solutions across the broadest range of consumer devices.|
High performance graphical processor providing advanced 2D and 3D acceleration Supports OpenGL ES 2.0
|Mali-300 GPU||High performance graphical processor providing advanced 2D and 3D acceleration Supports OpenGL ES 2.0 Cost-optimized version of Mali-400 GPU, limited to single shader processor and 8kB L2 cache|
|Mali-55GPU||The Mali-55 GPU is the world's smallest OpenGL ES 1.1 compliant GPU using the Mali tile-based rendering architecture to maximize the efficiency of energy usage in displaying graphical images and to minimize the bandwidth demands on the system|
|ARM® Physical IP Platforms deliver process optimized IP, for best-in-class implementations of the Cortex-A5 processor at 28nm and below.|
|Standard Cell Logic Libraries||Available in a variety of different architectures ARM Standard Cell Libraries support a wide performance range for all types of SoC designs. Designers can choose between different libraries and optimize their designs for speed, power and/or area|
|Memory Compilers and Registers||A broad array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications.|
|Interface Libraries||A broad portfolio of silicon-proven Interface IP designed to meet varying system architectures and standards. General Purpose I/O, Specialty I/O, High Speed DDR and Serial Interfaces optimized to deliver high data throughput performance with low pin counts.|
The ARM Development Studio 5 (DS-5™) tool suite, as well as a wide range of third party tools, operating system and EDA vendors support all ARM processors. ARM DS-5 software development tools are unique in their ability to provide solutions that take full advantage of the complete ARM technology portfolio.