The Cortex-A5 processor is the most mature, most configurable, smallest and lowest power ARMv7-A CPU. It provides a high-value migration path for existing ARM926EJ-S™ and ARM1176JZ-S™ processor designs. It achieves better performance than the ARM1176JZ-S processor, better power and energy efficiency than the ARM926EJ-S, and 100% Cortex-A compatibility.
These processors deliver high-end features to power and cost-sensitive applications, featuring:
The Cortex-A5 is designed for applications that require virtual memory management for high-level operating systems within an extremely low power profile.
|Mobile||Entry-level Smartphones, Feature Phones, Mobile Payments, Audio|
|Home/Consumer||Digital TV, DVD|
|Embedded/Industrial||MPU, Smart Meters, IoT, Wearable Devices|
As ARM's most energy-efficient ARMv7 applications processor, the Cortex-A5 gets more work done per unit of energy. This corresponds to longer battery life and less heat dissipation in wearable and mobile devices.
The tiny size of Cortex-A5 offers the following advantages:
The Cortex-A5 processor provides full instruction and feature compatibility with the higher performance Cortex-A8 and Cortex-A9 processors at one-third of the area and power. The Cortex-A5 processor also maintains backwards application compatibility with Classic ARM processors including the ARM926EJ-S, ARM1176JZ-S, and ARM7TDMI®.
ARM Cortex-A5 Performance, Power, and Area (PPA)
|TSMC 40LP||TSMC 40G|
|Process Type/Nominal Voltage||low leakage, 1.1V||performance, 1.0V|
|Performance or Frequency Optimized||Frequency||Frequency|
|Frequency||530~600 MHz (all RVt)
700MHz + with LVt
|Area excluding RAMs/cache||0.27mm²||0.27mm²|
|Area with 16K/16K cache||0.53mm²||0.53mm²|
|Area with 16K/16K cache + NEON||0.68mm²||0.68mm²|
|Dynamic Power||0.12 mW/MHz||<0.08mW/MHz|
|Energy Efficiency||13 DMIPS/mW||>20 DMIPS/mW|
The Cortex-A5 processor is designed to be a highly configurable processor. For example, the instruction and data cache sizes can be configured in the range of 4KB-64KB. The smallest configuration with 4KB caches can be as tiny as 0.2mm2 in 28nm process technology. This and other configurability options in Cortex-A5 (like optional FPU, NEON, etc) enable designers to make trade-offs for performance and cost for their targeted application.
|Dhrystone Performance||1.57 DMIPS / MHz per core|
Single core version also available
|Memory Management||ARMv7 Memory Management Unit|
|Debug & Trace||CoreSight™ DK-A5|
|Cortex-A5 Key Features|
|NEON Media Processing Engine (MPE)||
|Floating Point Unit (FPU)||
|Configurable L1 Caches||
|High Performance AXI Bus||
|Advanced Multicore Technologies|
|Accelerator Coherence Port (ACP)||
|Generic Interrupt Controller (GIC)||
System IP components are essential for building complex system on chips and by utilizing them, developers can significantly reduce development and validation cycles, saving cost and reducing time to market.
|Description||AMBA Bus||System IP Components|
|Advanced AMBA 3 Interconnect IP||AXI||NIC-400, PL301|
|DMA Controller||AXI||DMA-330 , PL330|
|Level 2 Cache Controller||AXI||L2C-310 , PL310|
|Dynamic Memory Controller||AXI||DMC-340 , PL340|
|DDR2 Dynamic Memory Controller||AXI||DMC-342|
|Static Memory Controller||AXI||SMC-35x , PL35x|
|TrustZone Address Space Controller||AXI||PL380|
|CoreSight™ Design Kit||ATB||CDK-11|
|The Mali™ family of products combine to provide the complete graphics stack for all embedded graphics needs, enabling device manufacturers and content developers to deliver the highest quality, cutting edge graphics solutions across the broadest range of consumer devices.|
The world's first OpenGL® ES 2.0 conformant multi-core GPU provides 2D and 3D acceleration with performance scalable up to 1080p resolutions, while maintaining ARM leadership on power and bandwidth efficiency
|ARM® Physical IP Platforms deliver process optimized IP, for best-in-class implementations of the Cortex-A5 processor at 28nm and below.|
|Standard Cell Logic Libraries||Available in a variety of different architectures ARM Standard Cell Libraries support a wide performance range for all types of SoC designs. Designers can choose between different libraries and optimize their designs for speed, power and/or area|
|Memory Compilers and Registers||A broad array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications.|
|Interface Libraries||A broad portfolio of silicon-proven Interface IP designed to meet varying system architectures and standards. General Purpose I/O, Specialty I/O, High Speed DDR and Serial Interfaces optimized to deliver high data throughput performance with low pin counts.|
Cortex-A5 processors are fully supported by ARM DS-5 Development Studio as well as a wide range of third party tools, operating systems and EDA flows. DS-5 represents a comprehensive range of software tools to create, debug and optimize systems based on the Cortex-A5 processor.
It incorporates DS-5 Debugger, whose powerful and intuitive graphical environment enables fast debugging of bare-metal, Linux and Android native applications. DS-5 Debugger provides pre-defined configurations for Fixed Virtual Platforms (built on ARM Fast Models technology) and ARM Versatile Express boards, enabling early software development before silicon availability.
In addition, Streamline performance analyzer simplifies the identification of hot spots in software and load balancing between cores and clusters with a brilliantly intuitive graphical display.
ARM Compiler 5 includes specific optimizations for the Cortex-A5 processor, enabling code generation from the earliest stages of your project and is included in DS-5.
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