Cortex-A5 Processor

Cortex-A5 Processor Image (View Larger Cortex-A5 Processor Image)
The ARM® Cortex®-A5 processor is the smallest, lowest cost and lowest power ARMv7 application processor, ideal as a stand-alone processor within current and future generations of smart wearable devices. It is capable of delivering the internet to the widest possible range of devices, from smart devices like wearables, feature phones and low-cost, entry-level smartphones, to a range of pervasive embedded, consumer and industrial devices. 






The Cortex-A5 processor is the most mature, most configurable, smallest and lowest power ARMv7-A CPU. It provides a high-value migration path for existing ARM926EJ-S™ and ARM1176JZ-S™ processor designs. It achieves better performance than the ARM1176JZ-S processor, better power and energy efficiency than the ARM926EJ-S, and 100% Cortex-A compatibility.

These processors deliver high-end features to power and cost-sensitive applications, featuring:

  • Multiprocessing capability for scalable, energy-efficient performance
  • Optional Floating Point Unit (FPU) or NEON™ units for media and signal processing
  • Full application compatibility with the Cortex-A8, Cortex-A9, and Classic ARM processors
  • High performance memory system including caches and Memory Management Unit (MMU) 


The Cortex-A5 is designed for applications that require virtual memory management for high-level operating systems within an extremely low power profile.

Product Type Application
Mobile Entry-level Smartphones, Feature Phones, Mobile Payments, Audio
Home/Consumer Digital TV, DVD
Embedded/Industrial MPU, Smart Meters, IoT, Wearable Devices

Area and Energy Efficiency

The Cortex-A5 is the smallest and lowest power applications processor, delivering rich functionality to high-performance wearables

As ARM's most energy-efficient ARMv7 applications processor, the Cortex-A5 gets more work done per unit of energy. This corresponds to longer battery life and less heat dissipation in wearable and mobile devices.

The tiny size of Cortex-A5 offers the following advantages:

  • Lowers manufacturing cost
  • Allows more low-cost integration
  • Reduces leakage


The Cortex-A5 processor provides full instruction and feature compatibility with the higher performance Cortex-A8 and Cortex-A9 processors at one-third of the area and power. The Cortex-A5 processor also maintains backwards application compatibility with Classic ARM processors including the ARM926EJ-S, ARM1176JZ-S, and ARM7TDMI®.

ARM Cortex-A5 Performance, Power, and Area  (PPA)

Process Type/Nominal Voltage low leakage, 1.1V performance, 1.0V
Performance or Frequency Optimized Frequency Frequency
Frequency 530~600 MHz (all RVt)
700MHz + with LVt
Area excluding RAMs/cache 0.27mm² 0.27mm²
Area with 16K/16K cache 0.53mm² 0.53mm²
Area with 16K/16K cache + NEON 0.68mm² 0.68mm²
Dynamic Power 0.12 mW/MHz <0.08mW/MHz
Energy Efficiency 13 DMIPS/mW >20 DMIPS/mW
  • Core area, frequency range, and power consumption are heavily dependent on processes, libraries and optimizations.
  • The numbers quoted above are illustrative of synthesized cores using general purpose process technologies and ARM standard cell libraries and RAMs.

Floorplan snapshot for Cortex-A5 processor

PPA reporting conditions:

  • ARM High Performance SC12 logic library and performance RAMs
  • Frequency optimized
  • 85% Utilization
  • Frequency at Slow Silicon/Vdd-10% (1.0V)/125C10% OCV and 50ps clock uncertainty
  • Dhrystone power for typical conditions/Vdd (1.1V)/25C
  • All regular Vt transistors

The Cortex-A5 processor is designed to be a highly configurable processor. For example, the instruction and data cache sizes can be configured in the range of 4KB-64KB. The smallest configuration with 4KB caches can be as tiny as 0.2mm2 in 28nm process technology. This and other configurability options in Cortex-A5 (like optional FPU, NEON, etc) enable designers to make trade-offs for performance and cost for their targeted application.

Architecture ARMv7-A Cortex
Dhrystone Performance 1.57 DMIPS / MHz per core
Multicore 1-4 cores
Single core version also available
ISA Support
Memory Management ARMv7 Memory Management Unit
Debug & Trace CoreSight™ DK-A5

Cortex-A5 Key Features
Thumb-2 Technology
  • Delivers the peak performance of traditional ARM code while also providing up to a 30% reduction in memory required to store instructions
TrustZone® Technology
  • Ensures reliable implementation of security applications ranging from digital rights management to electronic payment. Broad support from technology and industry Partners.
NEON Media Processing Engine (MPE)
  • The optional Cortex-A5 NEON MPE provides both the performance and functionality of the Cortex-A5 Floating Point Unit plus an implementation of the ARM NEON Advanced SIMD instruction set for further acceleration of media and signal processing functions
  • The MPE extends the Cortex-A5 Floating Point Unit (FPU) an additional register set supporting a rich set of SIMD operations over 8, 16, and 32-bit integer and 32-bit floating point data types.
Floating Point Unit (FPU)
  • The optional Cortex-A5 FPU is an implementation of the ARM Vector Floating Point v4 architecture, with 16 double-precision registers (VFPv4-D16).
  • The unit provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic (IEEE 754).
  • The FPU supports all data-processing instructions and data types in the VFPv4 architecture and fully supports single-precision and double-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations.
  • The FPU also provides conversions between fixed-point and floating-point data formats, and floating-point constant instructions.
Configurable L1 Caches
  • The power optimized L1 instruction and data Caches are individually configurable from 4-64K. Optimized instances of ARM SRAMs are available for Cortex-A5 processor.
High Performance AXI Bus
  • The Cortex-A5 implements a 64-bit unified AXI bus that supports multiple outstanding transactions, and has over 3x the memory bandwidth of the ARM1176JZ-S.

Advanced Multicore Technologies
  • Snoop Control Unit (SCU)
  • The SCU is the central intelligence in the ARM multicore technology and is responsible for managing the interconnect, arbitration, communication, cache-2-cache and system memory transfers, cache coherence and other capabilities for all multicore technology enabled processors.
  • The Cortex-A5 MPCore processor also exposes these capabilities to other system accelerators and non-cached DMA driven mastering peripherals so as to increase the performance and reduce the system wide power consumption by sharing access to the processor's cache hierarchy.
  •  This system coherence also reduces the software complexity involved in otherwise maintaining software coherence within each OS driver.
Accelerator Coherence Port (ACP)
  • This AMBA® 3 AXI™ compatible slave interface on the SCU provides an interconnect point for a range of system masters that - for overall system performance, power consumption or reasons of software simplification - are better interfaced directly with the Cortex-A5 MPCore processor.
  • The interface acts as a standard AMBA 3 AXI slave, and supports all standard read and write transactions without any additional coherence requirements placed on attached components.
  • However, any read transactions to a coherent region of memory will interact with the SCU to test whether the required information is already stored within the processor L1 caches. If it is, it is returned directly to the requesting component.If it missed in the L1 cache, then there is also the opportunity to hit in L2 cache before finally forwarding to the main memory.
  • For write transactions to any coherent memory region, the SCU will enforce coherence before forwarding the write to the memory system. The transaction may also optionally allocate into the L2 cache thus removing the power and performance impact of writing directly through to the off chip memory.
Generic Interrupt Controller (GIC)
  • Implementing the recently standardized and architected ARM interrupt controller, the GIC provides a rich and flexible approach to inter-processor communication and the routing and prioritisation of system interrupts.
  •  Supporting up to 224 independent interrupts under software control, each interrupt can be distributed across CPU, hardware, prioritized and routed between the operating system and TrustZone software management layer.
  •  This routing flexibility and the support for virtualization of interrupts into the operating system, provides one of the key features required to enhance the capabilities of a solution utilizing a paravirtualization manager.

Commonly integrated with other IP blocks, the Cortex-A5 is the centerpiece of many next-generation devices.

System IP

System IP components are essential for building complex system on chips and by utilizing them, developers can significantly reduce development and validation cycles, saving cost and reducing time to market.

Description AMBA Bus System IP Components
Advanced AMBA 3 Interconnect IP AXI NIC-400, PL301
DMA Controller AXI DMA-330 , PL330
Level 2 Cache Controller AXI L2C-310 , PL310
Dynamic Memory Controller AXI DMC-340 , PL340
DDR2 Dynamic Memory Controller AXI DMC-342
Static Memory Controller AXI SMC-35x , PL35x
TrustZone Address Space Controller AXI PL380
CoreSight™ Design Kit ATB CDK-11

Media Processors
The Mali™ family of products combine to provide the complete graphics stack for all embedded graphics needs, enabling device manufacturers and content developers to deliver the highest quality, cutting edge graphics solutions across the broadest range of consumer devices.
Mali-400 GPU

The world's first OpenGL® ES 2.0 conformant multi-core GPU provides 2D and 3D acceleration with performance scalable up to 1080p resolutions, while maintaining ARM leadership on power and bandwidth efficiency

Physical IP
ARM® Physical IP Platforms deliver process optimized IP, for best-in-class implementations of the Cortex-A5 processor at 28nm and below.
Standard Cell Logic Libraries Available in a variety of different architectures ARM Standard Cell Libraries support a wide performance range for all types of SoC designs. Designers can choose between different libraries and optimize their designs for speed, power and/or area
Memory Compilers and Registers A broad array of silicon proven SRAM, Register File and ROM memory compilers for all types of SoC designs ranging from performance critical to cost sensitive and low power applications.
Interface Libraries A broad portfolio of silicon-proven Interface IP designed to meet varying system architectures and standards. General Purpose I/O, Specialty I/O, High Speed DDR and Serial Interfaces optimized to deliver high data throughput performance with low pin counts.

Development Tools for Cortex-A5

Cortex-A5 processors are fully supported by ARM DS-5 Development Studio as well as a wide range of third party tools, operating systems and EDA flows. DS-5 represents a comprehensive range of software tools to create, debug and optimize systems based on the Cortex-A5 processor.

It incorporates DS-5 Debugger, whose powerful and intuitive graphical environment enables fast debugging of bare-metal, Linux and Android native applications. DS-5 Debugger provides pre-defined configurations for Fixed Virtual Platforms (built on ARM Fast Models technology) and ARM Versatile Express boards, enabling early software development before silicon availability.

In addition, Streamline performance analyzer simplifies the identification of hot spots in software and load balancing between cores and clusters with a brilliantly intuitive graphical display.

ARM Compiler 5 includes specific optimizations for the Cortex-A5 processor, enabling code generation from the earliest stages of your project and is included in DS-5.


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