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Cortex-M0 Processor

Cortex-M0 Processor Image (View Larger Cortex-M0 Processor Image)
The ARM Cortex®-M0 processor is the smallest ARM processor available. The exceptionally small silicon area, low power and minimal code footprint of the processor enables developers to achieve 32-bit performance at an 8-bit price point, bypassing the step to 16-bit devices. The ultra-low gate count of the Cortex-M0 processor also enables its deployment in analog and mixed signal devices.
 


The smallest ARM processor

The code density and energy efficiency benefits of Cortex-M0 mean that it is a natural and cost effective successor to 8/16-bit devices in a wide variety of applications, while retaining tool and binary upwards compatibility with the feature-rich Cortex-M3 and Cortex-M4 processors. For applications requiring even lower consumption or a wider choice of design options, the fully compatible Cortex-M0+ processor is an ideal alternative.

Low power  

The Cortex-M0 processor, which consumes as little as 16µW/MHz (90LP process, minimal configuration) in an area of under 12 K gates, builds on the unrivalled expertise of ARM as a leader in low-power technology and a key enabler for the creation of ultra low-power devices.

Simplicity

With just 56 instructions, it is possible to master quickly the entire Cortex-M0 instruction and its C friendly architecture, making development simple and fast. The option for fully deterministic instruction and interrupt timing makes it easy to calculate response times.

Optimized connectivity

Designed to support low power connectivity such as Bluetooth Low Energy (BLE), IEEE 802.15 and Z-wave, particularly in analog devices that are increasing their digital functionality to pre-process and communicate data efficiently.


ARM Cortex-M0 Specifications

ARM Cortex-M0 Features
ISA Support Thumb® / Thumb-2 subset
Pipeline 3-stage
Performance Efficiency 2.33 CoreMarks/MHz* 
Performance Efficiency 0.84 / 0.99 / 1.21 DMIPS/MHz**
Interrupts Non-maskable Interrupt (NMI) + 1 to 32 physical interrupts
Sleep Modes Integrated WFI and WFE Instructions and Sleep On Exit capability
Sleep & Deep Sleep Signals
Optional Retention Mode with ARM Power Management Kit
Bit Manipulation Bit banding region can be implemented with Cortex-M System Design Kit
Enhanced Instructions Hardware single-cycle (32x32) multiply option
Debug Optional JTAG or Serial-Wire Debug Ports. Up to 4 Breakpoints and 2 Watchpoints

* see: http://www.eembc.org/benchmark/reports/benchreport.php?benchmark_seq=1509&suite=CORE

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhrystone

ARM Cortex-M0 Implementation Data***
180ULL
7-track, typical 1.8v, 25C)
90LP
7-track, typical 1.2v, 25C)
40G
9-track, typical 0.9v, 25C)
Dynamic Power 73µW/MHz 16µW/MHz 4µW/MHz
Floorplanned Area 0.13 mm2 0.04 mm2 >0.01 mm2

*** Base usable configuration includes 1 IRQ + NMI, excludes debug


ARM Cortex-M technologies

Each Cortex-M series processor delivers specific benefits, underpinned by fundamental technologies that make Cortex-M processors ideal for a broad range of embedded applications.


RISC processor core Thumb-2® technology
  • High performance 32-bit CPU
  • Deterministic operation
  • Compact, low latency pipeline
  • Optimal blend of 16/32-bit instructions
  • 30% smaller code size than 8-bit devices
  • No compromise on performance

Tools and RTOS support CoreSight debug and trace

Low power modes Nested Vectored Interrupt Controller (NVIC)
  • Integrated sleep state support
  • Multiple power domains
  • Architected software control
  • Low latency, low jitter interrupt response
  • No need for assembly programming
  • Interrupt service routines in pure C

CMSIS

The ARM Cortex Microcontroller Software Interface Standard (CMSIS) is a vendor-independent hardware abstraction layer for the Cortex-M processor series.The CMSIS enables consistent and simple software interfaces to the processor for interface peripherals, real-time operating systems, and middleware, simplifying software re-use. With a reduced learning curve for new microcontroller developers, CMSIS shortens the time to market for new products.

In-depth: Nested Vectored Interrupt Controller (NVIC)

The NVIC is an integral part of all Cortex-M processors and provides the processors' outstanding interrupt handling abilities. In the Cortex-M0, Cortex-M0+ and Cortex-M1 processors, the NVIC support up to 32 interrupts (IRQ), a Non-Maskable Interrupt (NMI) and various system exceptions. The Cortex-M3 and Cortex-M4 processors extend the VIC to support up to 240 IRQs, 1 NMI and further system exceptions.

Most of the NVIC settings are programmable. The configuration registers are part of the memory map and can be accessed as C pointers. The CMSIS library also provided various helper functions to make interrupt control easier.
Inside the NVIC, each interrupt source is assigned an interrupt priority. A few of the system exceptions like such as NMI haves a fixed priority level, and others hashave programmable priority levels. By assigning different priorities to each interrupt, the NVIC can support Nested Interrupts automatically without any software intervention.

The architecture provides 8-bits of priority level settings for each programmable interrupt or exception. To reduce gate count, only parts of these registers are implemented. In the Cortex-M0, Cortex-M0+ and Cortex-M1 processors (ARMv6-M architecture), 4 programmable levels are provided. In the Cortex-M3 and Cortex-M4 processors (ARMv7-M architecture), the designs allow from 8 priority levels to 256 levels.

To make the Cortex-M processors easier to use, the Cortex-M processor uses a stack based exception model. When an exception takes place a number of registers are pushed on to the stack. These registers are restored to their original values when the exception handler completes. This allows the exception handlers to be written as normal C functions, and also reduce the hidden software overhead ofin interrupt processing.

In addition, the Cortex-M processors use a vector table that contains the address of the function to be executed for eacha particular interrupt handler. On accepting an interrupt, the processor fetches the address from the vector table. Again, this avoids software overhead and reduces interrupt latency.

Various optimization techniques are also used in the Cortex-M processor implementationss to make interrupt processing more efficiency and make the system more responsive:

Tail chaining – If another exception is pending when an ISR exits, the processor does not restore all saved registers from the stack and instead moves on to the next ISR. This reduces the latency when switching from one exception handler to another.

Stack pop pre-emption – If another exception occurs during the unstacking process of an exception, the processor abandons the stack Pop and services the new interrupt immediately as shown above. By pre-empting and switching to the second interrupt without completing the state restore and save, the NVIC achieves lower latency in a deterministic manner.

Late arrival – If a higher priority interrupt arrives during the stacking of a lower priority interrupt, the processor fetches a new vector address and processes the higher priority interrupt first.

With these optimizations, the interrupt overhead reduces as the interrupt loading increases, allowing high interrupt processing throughput in embedded systems.


ARM Cortex-M code size advantage explained

ARM Cortex-M processors offer superior code density to 8-bit and 16-bit architectures. This has significant advantages in terms of reduced memory requirements and maximizing the usage of precious on-chip Flash memory. In this section we examine the reasons for this advantage.

Instruction width

It is a common misconception that 8-bit microcontrollers use 8-bit instructions and ARM Cortex-M processor-based microcontrollers use 32-bit instructions. In reality for example, the PIC18 and PIC16 instruction sizes are 16-bit and 14-bit respectively. For the 8051 architecture, although some instructions are 1 byte long, many others are 2 or 3 bytes long. The same also applies to 16-bit architectures, where some instructions can take 6 bytes or more of memory.

The ARM Cortex-M processors utilize the ARM Thumb®-2 technology which provides excellent code density. With Thumb-2 technology, the Cortex-M processors support a fundamental base of 16-bit Thumb instructions, extended to include more powerful 32-bit instructions. In many cases a C compiler will use the 16-bit version of the instruction unless the operation can be carried out more efficiently using a 32-bit version.

Instruction efficiency

This picture is not complete without also considering that ARM Cortex-M processor instructions are more powerful. There are many circumstances where a single Thumb instruction equates to several 8/16-bit microcontroller instructions; this means that Cortex-M devices have smaller code and achieve the same task at lower bus speed.

Comparing 16-bit multiply operations across processor architectures


8-bit example 16-bit example ARM Cortex-M

MOV A, XL ; 2 bytes

MOV B, YL ; 3 bytes

MUL AB; 1 byte

MOV R0, A; 1 byte

MOV R1, B; 3 bytes

MOV A, XL ; 2 bytes

MOV B, YH ; 3 bytes

MUL AB; 1 byte

ADD A, R1; 1 byte

MOV R1, A; 1 byte

MOV A, B ; 2 bytes

ADDC A, #0 ; 2 bytes

MOV R2, A; 1 byte

MOV A, XH ; 2 bytes

MOV B, YL ; 3 bytes

MUL AB; 1 byte

ADD A, R1; 1 byte

MOV R1, A; 1 byte

MOV A, B ; 2 bytes

ADDC A, R2 ; 1 bytes

MOV R2, A; 1 byte

MOV A, XH ; 2 bytes

MOV B, YH ; 3 bytes

MUL AB; 1 byte

ADD A, R2; 1 byte

MOV R2, A; 1 byte

MOV A, B ; 2 bytes

ADDC A, #0 ; 2 bytes

MOV R3, A; 1 byte

MOV R4,&0130h

MOV R5,&0138h

MOV SumLo,R6

MOV SumHi,R7

(Operands are moved to and from a memory mapped hardware multiply unit)

MULS r0,r1,r0

N.B. The Cortex-M multiply in fact performs a 32-bit multiply, here we assume r0 and r1 contain 16-bit data.

Compact data footprint

It is important to note that Cortex-M processors have support for 8-bit and 16-bit data tranfers, making efficient use of data memory. This means programmers can continue to use the same data-types as they have in 8/16-bit targeted software.

Energy efficiency advantage

The demand for ever lower-cost products with increasing connectivity (e.g. USB, Bluetooth, IEEE 802.15) and sophisticated analog sensors (e.g. accelerometers, touch screens) has resulted in the need to more tightly integrate analog devices with digital functionality to pre-process and communicate data. Most 8-bit devices do not offer the performance to sustain these tasks without significant increases in MHz and therefore power, and so embedded developers are required to look for alternative devices with more advanced processor technology. The 16-bit devices have previously been used to address energy efficiency concerns in microcontroller applications. However, the relative performance inefficiencies of 16-bit devices mean they will generally require a longer active duty cycle or higher clock frequency to accomplish the same task as a 32-bit device.

Ease of software development

Software development for ARM Cortex processor-based microcontrollers can be much easier than for 8-bit microcontroller products. Not only is the Cortex processor fully C programmable, it also comes with various enhanced debug features to help locating problems in software. There are also plenty of examples and tutorials on the internet, including many from ARM processor-based MCU vendor's websites, alongside any additional resources included in MCU development kits.


In this section you will find useful documentation, white papers and tutorials on ARM Cortex-M processors and related technologies. For further information including information on development tools, software, boards, and a device database, CMSIS and mBed visit the ARM Embedded Microsite.

ARM Connected Community

Cortex-M0 related blogs, discussions, technical content

Books

Definitive Guide to the ARM Cortex-M0
A comprehensive guide to programming and implementing the groundbreaking ARM Cortex-M0 processor
Definitive Guide to the ARM Cortex-M3
A comprehensive guide to programming and implementing the groundbreaking ARM Cortex-M3 processor

Documentation for Cortex-M device users

Software development tools for Cortex-M device users

Find Cortex-M based microcontrollers

Universities

Related User Guides and App Notes

Cortex-M0/3/4 Devices Generic User Guides

Instruction Timing Information

Architecture (requires registration)

ARM Application Notes

Keil Application Notes

DesignStart for Processor IP


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