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Virtualization Extensions

The ARM Architecture virtualization extension and Large Physical Address Extension (LPAE) enable the efficient implementation of virtual machine hypervisors for ARM architecture compliant processors. 

To handle complex software with potentially large amounts of data, connected consumer devices and cloud computing demand energy efficient, high performance systems.

The visualization extensions provide the basis for ARM architecture compliant processors to address the needs of both client and server devices for the partitioning and management of complex software environments into virtual machines.

The Large Physical Address extension provides the means for each of the software environments to utilize efficiently the available physical memory when handling large amounts of data.

As the complexity of software increases, the requirement for multiple software environments to be available on the same physical processor increases simultaneously. Software applications that require separation for reasons of isolation, robustness or differing real-time characteristics need a virtual processor exhibiting the required functionality.

To provide virtual processors in an energy-efficient manner requires a combination of hardware acceleration and efficient software hypervisors. The ARM Architecture Virtualization Extension standardizes the architecture for implementation of the hardware acceleration in ARM application processor cores, while high performance hypervisors from the world’s leading virtualization companies provide the software component upon which to build effective software combinations.

Cloud computing and other data or content oriented solutions increase the demands on the physical memory system from each virtual machine. The large physical address extensions provide a second level of MMU translation table so that each 32-bit virtual memory address mapped is within a 40-bit physical memory range. This allows systems to allocate sufficient physical memory to each virtual machine to maintain efficient throughput when total demands on memory exceed the range of 32-bit addressing.

 
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