The AMBA 3 AXI interface is the high performance on-chip interface specification available on the advanced ARM cores including the ARM1156T2-STM processor, the ARM1176JZ-STM processor, the ARM11TM MPCoreTM symmetric multiprocessor, the CortexTM-A8 and Cortex-R4 processors. The AMBA 3 AXI interface enables the easy creation of efficient, high frequency designs which maximize the use of interconnect resources leading to very high data-throughput. It also provides support for related ARM technologies such as IEM for voltage and frequency scaling and TrustZone® technology for system security applications such as DRM.
ARM has developed a suite of products to support the AMBA 3 AXI interface specification. | ARM Product | Description | TRM | | L220 | Level-2 Cache Controller | (995K PDF) | | PL301 | Configurable AXI Interconnect Fabric | 1 | | PL330 | Configurable AXI DMA Controller | 1 | | PL340 | Configurable Dynamic Memory Controller | (581K ZIP) | | PL341 | DDR2 Dynamic Memory Controller | (848K PDK) | | PL350 | Configurable Static Memory Controller | (1M PDF) | | PL390 | Generic Interrupt Controller | 1 |
Note 1 - Please contact ARM for access to these documents
The AMBA 3 AXI PrimeCell products are pre-verified, configurable AMBA 3 AXI system components that can be used to create a high-performance AMBA 3 AXI backplane. This AMBA 3 AXI backplane provides an optimized link from the processor core, through the cache and memory controllers to external memory. This unleashes the full performance of the ARM11 and Cortex family processors, even when used with low-cost slow external memory. 
The PrimeCell AXI Level-2 Cache Controller typically increases system performance from 50 percent to over 100 percent, by storing recently-used data in high-speed on chip memory. It can also reduce overall system power consumption, by reducing the number of power-hungry off-chip memory accesses and enable the use of a less costly external memory system. The PrimeCell AXI Configurable Interconnect provides a multi-layer topology that guarantees the necessary bandwidth and low latency for all connected IP blocks. The interconnect has a throughput of 1.6GB per layer at 200MHz and no limitation on the number of layers used. It comes with an XML specification that enables seamless integration into SPIRIT standard based EDA tools and drives the configuration of the AXI Configurable Interconnect to the specific requirements of the AMBA 3 AXI system. The PrimeCell AXI Static and Dynamic Memory Controllers efficiently interleave multiple outstanding accesses to main memory with up to twice the throughput yet only half the gate count of previous generation memory controllers. With their highly configurable architecture, the system designer can select the optimum balance of cost, size and performance to meet system requirements. Both the Static and Dynamic controllers are configurable to support a wide range of memory types and memory subsystem architectures. The AMBA PrimeCell Interrupt Controller portfolio provides a range of interfaces to the interrupt system and improves interrupt latency. AXI PrimeCell DMA controllers are devices that allow data to be transferred to or from memory or peripherals bypassing the system Central Processing Unit (CPU). This enables one of two possible outcomes; either it means that the CPU can be occupied with other potentially higher priority system tasks whilst the DMA controller ensures that no parts of the system starve from data shortages or the CPU can enter a low power mode for longer but with critical data still being transferred about the system. Back to Top | 
