Embedded Trace MacrocellsTM (ETM) provide comprehensive debug and trace facilities for ARM processors. They allow information on the processor's state to be captured both before and after a specific event, while adding no burden to the processor's performance, while the processor runs at full speed. The ARM Embedded Trace Macrocell family comprises the ETM7™, CoreSightTM ETM9™, ETM10RV TM, CoreSight ETM11™, and CoreSight ETMs available with the new Cortex-A8, Cortex-R4 and Cortex-M3 processors, see Table 2 below.
The Embedded Trace Macrocell can be configured in software to capture only select trace information and only after a specific sequence of conditions, see Table 1. A dedicated, configurable, trace port and FIFO then allow the compressed trace data to be read from the chip by an external trace port analyzer (RealView Trace unit) without interrupting, or effecting, the processor.
The trace port can be configured from a 1 to 32-bit data bus, with trace clock independent to the core clock. For example, the data rate from the ETM can be half of the core clock and the number of pins increased to maintain the data bandwidth. Similarly, the number of pins can be halved and the data rate increased.
CoreSight ETMs are designed for use both standalone and within a multi-core environment using the features of the CoreSight Design Kits to allow the developer to view simultaneous, correlated trace from multiple, asynchronous cores.
Table 1 - ETM Features and Sizes Feature | # | Address Comparators | 8 | Data Comparators | 2 | Address Range Comparators | 4 | 16-bit Counters | 2 | Three-stage Sequencer | 1 | External Inputs | 4 | External Outputs | 2* | ETM7 (medium) gate count estimate | 30k | Area of ETM7 in 0.18µm @ 100MHz | 0.34mm2 | ETM7 FIFO size in bytes | 20 | ETM9CS gate count estimate | 47k | Area of ETM9CS in 0.13µm @ 300MHz | 0.38mm2 | ETM9CS FIFO size in bytes | 60 | ETM10RV gate count estimate | 65k | Area of ETM10RV in 0.18µm @ 200MHz | 0.69mm2 | ETM10RV FIFO size in bytes | 64 | ETM11CS gate count estimate | 87k | Area of ETM11CS in 90nm @ 500MHz | 0.25mm2 | ETM11CS FIFO size in bytes | 72 | | ETM-A8 gate count estimate | 90k | | Area of ETM-A8 in 90nm @ 833MHz | 0.60mm2 | | ETM-A8 FIFO size in bytes | 128 | | ETM-R4 gate count estimate | 68k | | Area of ETM-R4 in 0.13um @ 300MHz | 0.42mm2 | | ETM-R4 FIFO size in bytes | 72 | | ETM-M3 gate count estimate | 7k | | Area of ETM-M3 in 0.13um @ 100MHz | 0.04mm2 | | ETM-M3 FIFO size in bytes | 16 |
Table 2 - ARM Processor Cores Supported ETM version | Processor | ETM7 | ARM7TDMI, ARM7TDMI-S, ARM720T, SC100 | ETM9 | ARM920T, ARM922T, ARM9TDMI, SC200 | | CoreSight ETM9 | ARM926EJ-S, ARM946E-S, ARM966E-S, ARM968E-S, ARM7EJ-S | ETM10RV | ARM1026EJ-S | CoreSight ETM11 | ARM1136J(F)-S, ARM1156T2(F)-S, ARM1176JZ(F)-S, ARM11 MPCore | | CoreSight ETM-R4 | Cortex-R4 | | ETM included with core (optional in synthesisable core) | Cortex-A8 | ETM included with core (optional) | Cortex-M3 |
NOTES
Areas are from trial synthesis, post layout.
ETM7 (medium) has only 1 external output.
Embedded Trace BufferTM (ETBTM)
The functionality of any of the Embedded Trace Macrocells (ETM) can be extended by the addition of an Embedded Trace Buffer (ETB).
The ETB is an on-chip memory area* where trace information is stored during capture rather than being exported immediately through a trace port at the pins of the device.The stored information can then be read out at a reduced clock rate from the ETB once capture has been completed. This is done through the JTAG port of the device. An application note (AN139) ARM RealView ETB Support gives details of recommended ETB and ETM ordering on the JTAG scan chain. This two step process removes the necessity for a wide trace port that uses many, high-speed device pins. Effectively, a “zero-pin” trace port is created where the device already has a JTAG port at the pins. The ETB can accept data at a higher frequency and with the full 32-bit data port, exceeding trace port bandwidth limitations. 
Software access to Trace Buffer
The buffered trace information can be accessed through an AMBA® AHBTM slave-based memory-mapped peripheral included as part of the ETB. When used with the CoreSight ETMs, the application code can carry out internal diagnostics on a closed system, without debugger attached. NOTE
The ETB integrates with a RAM block supplied by the system integrator. Back to Top | 
