Serial Wire Debug (SWD) Serial Wire Debug provides a debug port for severely pin limited packages, often the case for small package microcontrollers, but also on complex ASICs where limiting pincount is critical and can be the controlling factor in device costs. SWD replaces the 5-pin JTAG port with a clock + single bi-directional data pin, providing all the normal JTAG debug and test functionality plus real-time access to system memory without halting the core or requiring any target resident code. SWD uses an ARM standard bi-directional wire protocol, defined in the ARM Debug Interface v5, to pass data to and from the debugger and the target system in a highly efficient and standard way. As a standard interface for ARM-based devices, the software developer can count on a wide choice of interoperable tools from ARM and third party tool vendors. Only 2 pins required - vital for very low connectivity devices or packages Provides debug and test communication to JTAG TAP controllers Enables the debugger to become another AMBA bus master for access to system memory and peripheral or debug registers - High performance data rates - 640 Kbytes/sec @ 8 MHz
Low power - no extra power or ground pins required Small silicon area - 2.5k additional gates Low tools costs, <$100 build costs - may be built in to evaluation boards Reliable - built in error detection Safe - protection from glitches on pins when tools not connected
SWD provides an easy and risk free migration from JTAG as the two signals SWDIO and SWCLK are overlaid on the TMS and TCK pins, allowing for bi-modal devices that provide the other JTAG signals. These extra JTAG pins can be switched to other uses when in SWD mode. SWD is compatible with all ARM cores and any core using JTAG for debug and provides access to debug registers in Cortex cores and the CoreSight debug infrastructure. 
Serial Wire Viewer (SWV) Serial Wire Viewer provides a single pin output port for instrumentation trace. This allows the target resident code to communicate diagnostic information to the outside world through a single pin that might be all that is available on the final product form factor (e.g. the connector at the base of a mobile phone handset). - 32 virtual channels available to the application code
- simple, efficient packing and serializing protocol
- clock and data Manchester encoded in to a single output signal
- mode for connection to a standard UART
- ideal for data monitoring, viewing OS task switches, 'printf' debugging and call graph profiling
ARM Debug Interface v5 ARM introduced a new debug interface command set with the ARMv7 architecture, as used by the Cortex family of processors. This provides a new standard mechanism for providing debug access to all on-chip resources. The ADIv5 command set is common to both JTAG and Serial Wire Debug port options offered with ARM Cortex processors, and is compatible with existing ARM cores via the CoreSight Debug Access Port. - A unified channel to access debug components over a range of different bus standards.
- Maintains access to legacy components which provide a JTAG debug interface.
- Provides direct memory mapped access to system memory, independent of the core.
- Provides a low level common interface for system and debug power control.
- Allows the use of a standard 5-pin JTAG interface or a 2-pin Serial Wire Debug interface with a single port.
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