PrimeCell Level 2 Cache Controllers

Overview
The increase in performance in ARM's Processors has not been matched by the more modest performance increase in external memory devices. This can cause significant performance issues in applications, result in designs being limited by off-chip memory accesses and may even lead to system failures if critical memory accesses are not serviced in time.

By keeping the most commonly used data required by the Processor on-chip it is possible to reduce, or even eliminate, these problems.

Benefits
ARM has two PrimeCell Level-2 Cache Controller products that have been designed to address these issues.

These Controllers sit on-chip between the Processor and Memory Controller and enable reused data to be supplied quickly to the Processor and therefore eliminate the need to make costly external memory accesses. This can even help to reduce overall power consumption by minimizing relatively high power external memory accesses.

As an additional benefit, the number of transactions generated by the processor on the AMBA interconnect will be reduced by using a Level-2 cache controller thereby freeing the interconnect to be used by other on-chip devices.

As would be expected from PrimeCell Peripherals these products are designed and validated to the highest of standards, support the broadest range of industry tools and offer excellent value for money.

Portfolio
The PrimeCell Level-2 Cache Controllers are implemented to be compatible with all Processors using either the AMBA AXI or AHB protocols. The controllers can also be used to enable a simple 'drop-in' speed-up option to already architected systems struggling to meet system performance requirements.

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