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CoreLink AMBA Designer

CoreLink AMBA Designer Image (View Larger CoreLink AMBA Designer Image)
CoreLink™ AMBA Designer (ADR-301) makes it faster to configure and connect ARM Cortex™ AR and M class processors, Mali™ graphics hardware and AMBA IP, and applies captured designer knowledge when specifying configuration parameters in order to reduce risk.
 


Accelerating AMBA Protocol-Based Design

AMBA Designer FlowConfiguring and stitching together complex IP components manually is a time consuming process, which in turn introduces further complexity when ensuring the compatibility of interface parameters such as write interleaving and acceptance depths, bus widths, ID widths etc.

The ADR-301 tool provides a single common front end for configuring and integrating System IP and other ARM IP. The main benefits from this approach comprise rapid, error free configuration using intelligent configuration tools, and correct by construction connection of ports using the IP-XACT interface standard.

ADR-301 outputs configured Verilog RTL along with industry standard IP-XACT descriptions for ease of integration into third party design and implementation tools. Once a component is generated it can also be added to the ADR-301 component library to maximize re-use. Stitching together of multiple components is supported in a hierarchical manner. 

Comprehensive Set of Features Provided

Key Feature   Benefit 
Configuration Engines for System-IP which employ designer knowledge Rapid configuration of ARM AMBA components. Automatic checks for non-optimal and mutually exclusive configuration options always resulting in 'valid' configurations
GUI drag and drop integration environment Rapid assembly of configured AMBA components.
Industry standard IP-XACT 1.2 and 1.4 support

Maximizes re-use of existing configurations by allowing the user to create an IP library. Supports assembly and 'stitching' of ARM components and export of hierarchical components for the purpose of IP-XACT based top-level Verilog generation/stitching.

 

Outputs generated from ADR-301

From an IP Configuration Engine

  • A human-readable, fully commented set of optimized Verilog RTL modules
  • A test bench environment capable of demonstrating an 'out of box test' of the configured RTL module
  • An IP-XACT file representing the component instance that has been configured

Note: Although ADR-301 ships with all configuration engines, System IP is licensed separately from ADR-301 and requires a simple linking step during IP installation to enable RTL generation

 

From IP-XACT stitching

  • A top level Verilog file
  • A .VC file containing all of the Verilog module references
  • An IP-XACT file that can be used to start the stitching process at the next level of hierarchy

 

 


Features Summary

  • Provides configuration engines for AMBA IP which employs designer knowledge to automatically check for non-optimal and mutually exclusive configuration options
     
  • GUI drag and drop integration environment to allow for rapid assembly of configured PrimeCell components and even 3rd party imported components
     
  • Industry standard IP-XACT 1.2 and 1.4 support for imported components and busdefs for the purpose of IP-XACT based top level Verilog generation/stitching
     
  • Support for parsing top-level Verilog modules and generating IP-XACT 1.2 component definitions by auto identification and grouping of bus-signals into busdefs, manually over-ridden as required.

Benefits Summary

  • Rapid configuration of AMBA components from ARM
     
  • Rapid assembly of configured ARM Cortex AR and M series processors, Mali graphics hardware and AMBA IP components
     
  • Maximizes re-use of existing configurations by allowing the user to create an IP library

 

Main ADR-301 Components

The ADR-301 suite consists of a canvas and configurators.

The canvas is a graphical application that you can use to create new systems and modify existing ones. A system consists of leaf components or other sub-systems. You can create and manipulate systems using a graphical representation that shows the components, their ports, and the connections between ports. The picture of the ADR-301 canvas below breaks down into three main areas that are all inter-linked:

  1. The main drawing area of the canvas where components from the component library window are drag and dropped and their ports connected. Here designs are stitched together to generate top level Verilog and IP-XACT output
  2. Bottom left is the Configurator and hierarchy window. The hierarchy tab shown in the example allows the user to navigate more easily large designs by quickly identifying blocks and signals and 'zooming' in on selected items. The configurator window is described in the paragraph below.
  3. The user component library window, comprises a library of pre-configured component instances, which were either generated by a configurator, or imported from either a Verilog or an IP-XACT description. It is from this window that components can be drag and dropped onto the main drawing area for assembly/stitching.

Stitching an Osprey Subsystem (dual A9 cores)

 
The configurators tab, from the diagram above, provides a list of AMBA components that can be configured before generating RTL. See the related product tab on this page for a full list of AMBA components that are available. The diagram below shows a configurator window from an AMBA network interconnect NIC-301. The configurator here is showing the detailed topology inside a network interconnect configuration, and has color-coded each of the data widths.Note also the access paths available to a selected master, highlighted for readability.Other views provided by this configurator are architecture and address map views. Each configurator however will have its own layout depending on the complexity of the System IP is configuring.

 

Editing a NIC-301 r2 topology
 

As mentioned above, you can stitch together components and interconnects to generate top-level RTL modules for AMBA interconnect-based systems after executing the RTL generation from any given configurator. 

Note: ADR-301 ships with all supported configurators on a rolling update basis, if a configurator is not present for the Fabric System IP that you have recently purchased, you may need to update your ADR-301 installation. Note also that the RTL generation step is only available for each System IP that is licensed, downloaded and installed from ARM.  ADR-301 and System IP can be downloaded from https://connect.arm.com . Please note that you will need a connect Gold access license to download ADR-301 or any other System IP.


ADR-301 is also compatible with the following ARM System IP products:

Part Number Product Name Category

PL301

NIC-301 

AXI Network Interconnect

PL330

DMA-330 

AXI DMA Controller

PL340

DMC-340

AXI Dynamic Memory Controller (DDR)

PL341

DMC-341 

AXI Dynamic Memory Controller (DDR2)

PL342

DMC-342

AXI Dynamic Memory Controller (LPDDR2)

PL351

DMC-351 

Static Memory Controller

PL352

DMC-352 

Static Memory Controller

PL353

DMC-353 

Static Memory Controller

PL354

DMC-354 

Static Memory Controller

PL390

GIC-390

AXI Generic Interrupt Controller

PL230

DMA-230

AHB DMA Controller

BP010

BP010

AMBA AHB Development Kit (AHB BusMatrix Component)

PL310

L2C-310

Level 2 Cache Controller

PL380

TZC-380

TrustZone™ Address Space Controller

ADR-301 will enable configuration and stitching of the above components within its GUI environment. Because ADR-301 imports IP-XACT files for stitching, 3rd party components can also be imported for RTL stitching only.

Note: The BP010 is a development kit containing many discrete components. Only the AHB busmatrix component is configured using ADR-301

Verifying the Performance of your AMBA Interconnect

Once a NIC-301 component has been rendered, VPE-301 components can be instantiated onto each of its AXI interfaces for the purposes of performance exploration. Please see the VPE-301 product in this section for further details



Maximise


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