AMBA Designer (ADR-301)
- Making it easy and fast for designers to generate optimal ARM System IP
- Reducing 3 weeks of manual IP stitching to 3 days
Verification & Performance Exploration (VPE-301)
- Reducing 2M cycle Mali™200 test bench simulation from 4 hours to 4 minutes
- Giving a 300x performance boost over conventional functional verification IP
ADR-301 and VPE-301 in the Design Flow
The diagram below shows a design flow where the system architect starts with a spreadsheet analysis of a new or existing design. The further down the design flow, the greater the cost of iterating that phase of development. A combination of ADR-301 and VPE-301 early in the design flow allow more iterations at an earlier stage in the flow.
Once ARM System IP components are generated in ADR-301, VPE-301 provides realistic stimulus for enabling these choices, and reduces risks associated with making intuition-based decisions early on in the design cycle.
AMBA Design Tools Showcase Demonstrations
A demo at TechCon3 in October 2009 to illustrate ARMs commitment to building high performance, low power interconnect and memory controller solutions. These developments also combine with the AMBA Interconnect QoS product announcement during the same week.
A demo using VPE-301 at ARM DevCon 2008 to explore the performance of a network interconnect design for CPU latency testing. NIC-301 generated two configurations of ADR-301 and the relative performance was compared using VPE-301.