CoreLink Verification & Performance Exploration tool

CoreLink Verification & Performance Exploration tool Image (View Larger CoreLink Verification & Performance Exploration tool Image)
CoreLink™ VPE-301 is a tool that allows designers to optimize the performance of their AXI based System on chip in less time, using generated traffic profiles running in RTL simulation. VPE-301 executes much faster than real RTL masters but generates representative and controllable traffic.

Accelerating AMBA Protocol-Based Design

RTL top vs VPE bottomIncreasing SoC design complexity means on-chip fabric infrastructure is on the critical path to system performance. Efficient master to memory performance is key, with different masters having different requirements. Building and measuring system prototypes is a costly and time-consuming process for system designer and implementation teams.  

VPE-301 executes much faster than real RTL by ‘giving-up’ execution of functions within the substituted device in favor of emulating its traffic, and by replacing real data values with constrained random data.

In conclusion, for the purposes of system performance exploration, it takes significantly less development time to capture and reproduce realistic traffic profiles for different Systems IP using VPE-301 than it does to write a cycle-accurate model of the same device.

Complementing other Conventional Verification Tools

VPE-301 complements conventional verification tools in the following areas


Comprehensive Set of Features Provided

VPE-301 provides a comprehensive set of adaptable tools to stimulate and monitor AMBA 3 AXI interfaces at both block-level and system-level. VPE-301 enhances the verification process and enables you to keep control in a clear and simple way. It simplifies verification and speeds up the verification process. VPE-301 supports traditional functional verification, but also enables you to generate traffic profiles. Traffic profiles based on statistical distributions of selected AXI parameters include timing that you can either generate manually or collect from existing systems and then replay. 

Key Feature Benefit 
Performance exploration using traffic profiling Ease of system performance exploration using realistic traffic, speed of development of what-if scenarios, fast turnaround and high visibility without needing SystemC models, RTL or software components to be in place first
Channel-level directed traffic generation and checking Ease of reuse of bus functional model directed vectors
Transaction recording and visualization in simulator waveform view Makes it easier to build score-boarding and debug/decision making down to transaction level
Transaction recording and visualization Visibility of system performance at an early stage of development
Slave memory behavior Fully programmable slave memory device speeds up test bench generation and aids controllability
Protocol Checking and Coverage Monitoring Reduces risk by checking that AXI interfaces are protocol compliant at the same time as executing a minimum set of functionality corner-cases


Features Summary

  • AXI Monitor, AXI Master, AXI Slave components fully supporting the AMBA 3 AXI protocol
  • Traffic Profiling toolkit GUI (TPT) to generate & view traffic profiles
  • Includes Comprehensive AXI coverage points and AXI protocol checker in OVL and SVA formats

Benefits Summary

  • Provides both an AXI™ performance verification and a functional verification tool in one
  • Gives a measured 300x performance boost over conventional functional verification IP
  • Abstract away as much or as little of a system as required by attaching VPE-301 components to any AXI connection within a system
  • Is faster than developing a cycle-accurate System-C model for generating representative bus traffic
  • Is more accurate than Excel in that VPE-301 animates benchmarking data to bridge the gap between spreadsheet analysis and slow RTL simulation


Main VPE-301 Components

VPE-301 components contain user interfaces that enable you to access different levels in the AXI protocol stack, such as transaction, channel, and RTL signal levels. VPE-301 contains AXI master, AXI slave, and AXI monitor components that you can use for:

  • Functional verification by using directed vectors and TLM access to an AXI bus using a SystemVerilog interface.
  • Performance exploration by using the TPT to analyze captured statistical traffic profiles to modify and create new profiles for replay.

In this way, VPE-301 enables you to quickly identify and test system-level optimizations and opportunities for improvement. VPE-301 also contains an AXI protocol checker that contains OVL and SVA assertion libraries ensuring adherence to  AXI protocol. 

Algorithmic traffic generation

VPE-301 Masters and Slaves provide an optional Transaction Level Modeling (TLM) interface. This is a high-level interface that you can extend using SystemVerilog. You can develop your own algorithmic code at the transaction level using the TLM interface with SystemVerilog. You can create function calls to a set of functions that VPE-301 provides to enable you to develop tests quickly. VPE-301 performs the randomization of the traffic and the full protocol stack. You can add timing to the algorithmic code to represent a different type of micro-architecture.


Statistical profiled traffic generation

Statistical profiled traffic generation is derived from:

  • The concept of constrained random generation
  • Telecommunications models.

Traffic profiles statistically characterize the traffic, or transactions, on an AXI connection and represent IP traffic. Traffic flows are identifiable streams of traffic, or AXI transactions, between two points in a system, and represent the different streams or threads that the device issues. VPE-301 extends the concept of constrained random verification and applies this at the system level by adding mathematical modeling from the telecommunications industry.

You can define traffic profiles:

  • By using the GUI in the TPT 
  • By capturing them from a simulation.


The Traffic Profiling Toolkit (TPT)

You can use the TPT to: 

  • Create or adapt profiles
  • Analyze AXI traffic 

The traffic profile below shows and example of a profile populated by the VPE-301 monitor component with timing statistics from both read and write channels. The ITT histogram for example in the WRITE flow for device ID0 is showing the distribution in number of cycles between each write transaction. The first READ flow histogram for device ID0 is showing the distribution of read-initial-latency values in cycles. These are just two histograms from a wide range of available histograms covering all aspects of the AXI protocol.

You can create multiple flows in a profile, and characterize them by any payload parameter such as ID, or by attributes such as the address ranges accessed.

At this point, the traffic profile is retainable for analysis purposes or reusable in a VPE-301 Master or Slave component to define the shape of transactions and responses generated in the bus. Further fine-tuning can be applied to any histogram such as changing distribution of bursts, burst types, address ranges, etc., in order to answer what-if performance questions relating to the system or device under test. 

VPE Traffic profile window


Further analysis is possible on sampled traffic profiles, with the example below showing the analysis view tab within the TPT.The example below highlights bandwidth in MB/s from each master as well as number of data transfers.

VPE Analysis Window

Along with the analysis histograms shown above, the following analysis features are also provided as standard:

  • Data bus utilization
  • Read and write flow transfer latency summaries 
  • Profile payload summaries 
  • Read and write flow payload summaries. 

VPE-301 and ARM CoreLink system IP products:

Along with the ability to monitor or drive any standard AMBA AXI3 interface, VPE-301 is also compatible with the following ARM System IP products:

Part Number Product Name Category
FD001 ADR-301 AMBA configuration and stitching tool 
PL301 NIC-301  AXI Network Interconnect
PL330 DMA-330 AXI DMA Controller
PL340 DMC-340 AXI Dynamic Memory Controller (DDR)
PL341 DMC-341 AXI Dynamic Memory Controller (DDR2)
PL342 DMC-342 AXI Dynamic Memory Controller (LP-DDR2)
PL351 SMC-351 Static Memory Controller
PL352 SMC-352 Static Memory Controller
PL353 SMC-353 Static Memory Controller
PL354 SMC-354 Static Memory Controller
PL390 GIC-390 Generic Interrupt Controller


NIC-301 and VPE-301

Once a NIC-301 component has been configured and rendered using ADR-301, VPE-301 components can be instantiated onto each of its AXI interfaces for the purposes of performance exploration. Please see the VPE-301 product on this page for further details.



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