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AMBA Open Specifications

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The de facto standard for on-chip communication

The ARM® AMBA® protocol is an open standard, on-chip interconnect specification for the connection and management of functional blocks in a System-on-Chip (SoC). It facilitates right-first-time development of multi-processor designs with large numbers of controllers and peripherals. AMBA promotes design re-use by defining common interface standards for SoC modules.

AMBA 5 CHI (Coherent Hub Interface) specification is the latest addition to the AMBA family adding a new protocol for the highest performance, highly scalable SoCs required by many server and networking applications.

Issue E of AMBA 4 AXI and ACE protocol specification (Feb 2013) adds new optional properties for AXI ordering, ACE cache behavior and ARMv8 DVM messages for full cache coherency between processors.

For additional information on AMBA Specifications please see the AMBA FAQ Pages.

 


AMBA enables IP re-use

IP re-use is an essential component in reducing SoC development costs and timescales. AMBA specifications provide the interface standard that enables IP re-use if the following essential requirements are met:

Flexibility

IP re-use requires a common standard while supporting a wide variety of SoCs with different power, performance and area requirements. With its ACE, AXI, AHB and APB interface protocols, AMBA 4 has the flexibility to match every requirement. With AMBA 5 CHI interface ARM extends performance and scalability to many coherent processors.

Multi-Layer

The multi-layer architecture acts as a crossbar switch between masters and slaves in an AMBA 3 AXI or AHB system. The parallel links allow the bandwidth of the interconnect to support the peak bandwidth of the masters without increasing the frequency of the interconnect.

Compatibility

It is a standard interface specification that ensures compatibility between IP components from different design teams or vendors. The AMBA specifications are available as both a written specification as well as a set of assertions that unambiguously define the interface protocol, thus ensuring this level of compatibility.

Support

The wide adoption of AMBA specifications throughout the semiconductor industry has driven a comprehensive market in third party IP products and tools to support the development of AMBA based systems. The availability of SystemVerilog assertions for AMBApromote this industry wide participation.


AMBA 5 CHI Performance

The latest generation and highest performance AMBA 5 interface called CHI for Coherent Hub Interface is targeted at the highest performance, highly scalable SoCs found in networking and server applications. Support for:

  • Support for high frequency, non-blocking coherent data transfer between many processors
  • Quality of Service (QoS) to ensure optimal overall system performance across all masters
  • A layered model to allow separation of communication and transport protocols

AMBA 4 Performance

The AMBA 4 specification includes AXI4 and ACE (AXI Coherency Extensions). It is targeted at high bandwidth, high clock frequency system designs and includes features that make it suitable for high-speed deep sub-micron interconnect.  The key features and benefits of the AXI protocol are:

Support for cache coherency and enforced ordering

  • AXI Coherency Extensions (ACE) enable processors to snoop each other's caches
  • ACE-Lite enables media and I/O masters to snoop and keep coherent with the processors' caches
  • Barriers are broadcast to order multiple outstanding transactions to minimize stalling of the processor 

Allows implementations to reach higher clock frequencies by making it easy to re-time without losing throughput

  • Point-to-point channel architecture

Supports Globally-Asynchronous-Locally-Synchronous (GALS) techniques for large numbers of clock domains with variable frequencies.

  • Easy addition of register stages to achieve timing closure

A split channel architecture to increase throughput by taking full advantage of deeply pipelined SDRAM memory systems.

  • Burst based transactions with only start address issued
  • Issuing of multiple outstanding addresses
  • Out of order transaction completion
  • Separate address/control and data phases

AMBA 5 Specification

CHI

The AMBA 5 CHI (Coherent Hub Interface) architecture specification defines the interfaces for connection of fully coherent processors, such as the Cortex-A57 and Cortex-A53, and dynamic memory controllers, such as the CoreLink DMC-520, to high performance, non-blocking interconnects such as the CoreLink CCN-504.

It has been architected for scalability to maintain performance as the number of components and quantity of traffic rises. This includes placing additional requirements on masters to respond to coherent snoop transactions that means forward progress for particular masters can be more easily guaranteed in a congested system. The separation of the identification mechanism into master identifiers and transaction identifiers allows the interconnect to be constructed in a more efficient manner.

The CHI protocol provides a Quality of Service (QoS) mechanism to control how resources in the system shared by many processors are allocated without needing a detailed understanding of every component and how they might interact.

The CHI specification separates the protocol and transport layers to allow differing implementations to provide the optimal trade-off between performance, power and area.

The CHI specification is currently available to lead partners integrating SoCs or developing IP or tools that implement it. Please contact your ARM account manager for details on obtaining a copy.

AMBA 4 Specifications

The AMBA 4 specification adds another five interface protocols on top of the AMBA 3 specifications.

The AXI and ACE protocol specification Issue E, released February 2013, adds new optional properties for AXI ordering, ACE cache behavior and ARMv8 DVM messaging.

ACE

The ACE protocol, AXI Coherency Extensions, adds three new channels for sharing data between ACE master caches and hardware control of cache maintenance. ACE also adds barrier support to enforce ordering of multiple outstanding transactions, thus minimizing CPU stalls waiting for preceding transaction to complete. Distributed Virtual Memory (DVM) signaling maintains virtual memory mapping across multiple masters.

ACE-Lite

The ACE-Lite protocol is a small subset of ACE signals that offer I/O, or one-way, coherency, where ACE masters maintain the cache coherency of ACE-Lite masters.. ACE-Lite masters can still snoop ACE master caches, but other masters cannot snoop ACE-Lite master's caches. ACE-Lite also supports barriers.

AXI4

The AXI4 protocol is an update to AXI3 to enhance the performance and utilization of the interconnect when used by multiple masters. It includes the following enhancements:

  • Support for burst lengths up to 256 beats
  • Quality of Service signaling
  • Support for multiple region interfaces

AXI4-Lite

The AXI4-Lite protocol is a subset of the AXI4 protocol intended for communication with simpler, smaller control register-style interfaces in components. The key features of the AXI4-Lite interface are:

AXI4-Lite is a subset of the AXI4 protocol intended for communication with simpler, smaller control register-style interfaces in components. The key features of the AXI4-Lite interface are:
  • All transactions are burst length of one
  • All data accesses are the same size as the width of the data bus
  • Exclusive accesses are not supported

AXI4-Stream

The AXI4-Stream protocol is designed for unidirectional data transfers from master to slave with greatly reduced signal routing. Key features of the protocol are:

  • Supports single and multiple data streams using the same set of shared wires
  • Support for multiple data widths within the same interconnect
  • Ideal for implementation in FPGA

AMBA 3 Specifications

The AMBA 3 specification defines a set of four interface protocols that, between them, cover the on-chip data traffic requirements from data intensive processing components requiring high data throughput, low bandwidth communication requiring low gate count and power and on-chip test and debug access. The interfaces are:

AMBA 3 AXI Interface

The AMBA 3 AXI interface specification provides the characteristics to support highly effective data traffic throughput. The five unidirectional channels with flexible relative timing between them, and multiple outstanding transactions with out-of-order data capability enable:

  • Pipelined interconnect for high speed operation
  • Efficient bridging between frequencies for power management
  • Simultaneous read and write transactions
  • Efficient support of high initial latency peripherals

AMBA 3 AHB Interface

The AMBA 3 AHB interface specification enables highly efficient interconnect between simpler peripherals in a single frequency subsystem where the performance of AMBA 3 AXI is not required. Its fixed pipelined structure and unidirectional channels enable compatibility with peripherals developed for the AMBA 2 AHB-Lite specification.

AMBA 3 APB Interface

The AMBA 3 APB interface specification supports the low bandwidth transactions necessary to access configuration registers in peripherals and data traffic through low bandwidth peripherals. The highly compact and low power interface isolates this data traffic from the high performance AMBA 3 AHB and AMBA 3 AXI interconnects. The AMBA 3 APB interface is fully backwards compatible with the AMBA 2 APB interface allowing existing APB peripherals to be used.

AMBA 3 ATB Interface

The AMBA 3 ATB interface specification adds a data agnostic interface for trace data in a trace system to the AMBA specification. The trace components and bus sit in parallel with the peripherals and interconnect and provide visibility for debug purposes.

AMBA 2 Specifications

The AMBA 3 specification replaces AMBA 2 and should be used for new designs. Existing AMBA 2 peripherals can be used in an AMBA 3 based system. The AMBA 2 specification defines a set of two interface protocols:

AMBA 2 AHB Interface

The AMBA 2 AHB interface specification enables highly efficient interconnect between masters in a single frequency system. This interface includes all of the capabilities of the AMBA 3 AHB interface but also enables the use of arbitration between masters in the construction.

AMBA 2 APB Interface

The AMBA 2 APB interface specification supports the low bandwidth transactions necessary to access configuration registers in peripherals and data traffic through low bandwidth peripherals. The highly compact and low power interface isolates this data traffic from the high performance AMBA 2 AHB interconnect.


Protocol Checkers

ARM supplies System Verilog Assertions for AMBA 4 protocol checking.

Averant SolidPC employs a pre-defined set of technology rules to verify compliance with the AMBA AHB protocol specifications.

ARM Processors


Interface Interconnect Processors
CHI CoreLink CCN-504 Cortex-A57, Cortex-A53
ACE CoreLink CCI-400 Cortex™-A15, Cortex-A12, Cortex-A7
AXI CoreLink NIC-400, NIC-301 Cortex-A, Cortex-R, ARM1156, ARM1176
AHB CoreLink NIC-400, NIC-301, ADK Cortex-M, ARM1136, ARM9

ARM Connected Community

AMBA related blogs, discussions, technical content

Whitepapers

An Introduction to AMBA 4 ACE

Modeling and Verifying Cache-Coherent Protocols, VIP, and Designs - Jasper Design Automation and ARM collaborate to bolster ACE™ protocol deliverables

Downloads

The AMBA AXI3 Protocol CheckersAXI4 Protocol Checkers and ACE, ACE-Lite Protocol Checkers are available to registered ARM customers. Our Protocol Checkers include a full set of Protocol Assertions written in SystemVerilog (SVAs) with auxiliary logic to track temporal behaviour.

IP-XACT 1.4 Bus Definitions for AMBA 4 and AMBA 3 protocols are available to registered ARM customers.

Please ensure ARM's AMBA trademark license and usage guidelines are followed when using the AMBA brand.

In the documentation list below, the second version of the AMBA AXI Protocol Specification defines both AXI3, AXI4 and AXI4-Lite.

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Documentation

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