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CoreLink Cache Controllers

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AMBA® Level-2 Cache Controller designs boost performance of AMBA AHB and AXI processors while reducing overall traffic to system memory and therefore SoC energy consumption.

Overview

CPU to off-chip memory communication has become the performance bottleneck in many SoC. 

Level 2 Cache Controllers improve CPU performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip. At the same time, the reduced CPU demands on the off-chip memory bandwidth free up that resource for other masters. Level 2 Cache Controllers also contribute significantly to power efficiency as on-chip accesses are typically an order of magnitude lower in power versus going off-chip.

AMBA Level 2 Cache Controllers ,either ,embedded in the CPU or delivered as standalone components, are designed alongside the CPU to match the processor's requirements and easily integrate into AMBA AXI or AHB interconnects.

Product portfolio overview


Product Protocol Description Processors supported
 L2C-310  AXI A high performance AXI level 2 cache controller designed and optimized to address ARM latest AXI CPUs.  All AXI processors, in particular Cortex-A9, Cortex-A5, Cortex-R4, Cortex-R5, Cortex-R7, ARM11MPCore, ARM1176, ARM1156, Mali-200
 L2C-210 AHB A proven AHB level-2 cache controller designed to optimize ARM1136 and ARM926 based SoC. ARM1136, ARM926

L2C-310 for AMBA AXI processors

The L2C-310 is high performance AMBA AXI level 2 cache controller architected to optimize all AMBA AXI-based processors. Designed and optimized to operate with ARM latest high performance Cortex™ processors such the Cortex-A9 and Cortex-A5 processors, the L2C-310 delivers performance boost up to 250% when used with the Cortex-A9 processor (Figure 1).

The L2C-310 is a mature IP, widely licensed with the Cortex-A9 and Cortex-A5 processors and others ARM AXI processors, ARM demonstrated L2C-310 operating at 2Ghz part of the Cortex-A9 hard macro implementations.

While architected to deliver optimal performance with ARM AXI processors, L2C-310 can operate with any AXI masters and therefore re-use across many platforms.

Figure 1: L2C-310 with 256KB boosts Cortex-A9 performance by more than 200% when rendering web page

CortexA9 and L2C-310 Page Render Time

L2C-210 for AMBA AHB processors

The L2C-210 is a proven and technically mature AHB level-2 cache controller implemented in today's mass production ARM1136 and ARM926 based platforms, an example of such platform is the Freescale i.MX31.

Easy to integrate, the L2C-210 is the ideal answer to boosting the performance of AHB based ARM1136 and ARM926 platforms; the L2C-210 can  typically deliver performance boosts of up to 100% (Figure 2), enabling AHB platforms to deliver new class of services.

Figure 2:  MPEG4 Decode on ARM1136EJ-S Relative performance

L2C-210 boosts ARM1136

 
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