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CoreSight for Cortex-A Series Processors

CoreSight for Cortex-A Series Processors Image (View Larger CoreSight for Cortex-A Series Processors Image)
CoreSight™ for ARM Cortex™-A series processors provides embedded software and application developers with all the on-chip debug and real-time trace resources required for optimization and debug of Cortex-A application processor platforms.

 

 


CoreSight Design Kits for Cortex-A series processors (Cortex-A9, Cortex-A8, Cortex-A5) provide a complete infrastructure for optimization and debug of advanced platforms running OS and targeting applications, and requiring outstanding performance and low energy consumption.

Architected to debug & trace heterogeneous high performance multicore systems

CoreSight Design Kits for Cortex-A series processors give:

 Higher visibility through fewer pins

Powerful multi core interactive debugging with real-time visibility

CoreSight for Cortex-A series processors enable developers to control (debug) and observe (trace) their Cortex-A processor-based SoC with fewer pins. 
Cortex-A processor debug and run time control can be performed with only 2 pins using the Serial Wire Debug technology or alternatively using JTAG, when highly compressed real-time trace of the cores and others system trace can be captured on-chip (ETB) or exported through a dedicated trace port (TPIU).

 

With the CoreSight DAP and the Embedded Cross Triggering, developers can perform powerful symmetric and asymmetric multicore debug and run-time control, while collecting time stamped CPU or system trace to analyze, optimize and debug software and hardware interaction.

Visibility of program execution on multicore SoCs

Visibility for high performance, low energy and secure systems

CoreSight trace macrocells for Cortex processors give software developers vital information on how their software executes on the platform. All Cortex-A trace macrocells are OS aware enabling development tools to deliver OS aware debug and optimization. 

 

The CoreSight technology supports the highest performance processors while being architected to minimize energy consumption. The CoreSight technology provides SoC architects the flexibility to implement the most power efficient debug and trace solution, by enabling multi clock and power domains debug and real-time trace.
CoreSight also makes provision for secure debug and trace, enabling provision of this vital visibility only to trusted users.

Value to different users during the life of the SoC

Re-use & standardization

CoreSight technology is in use throughout the life of the SoC, enabling silicon suppliers and OEMs to decrease cost and development risks. CoreSight can be leveraged for other components in the SoC, enabling Partners to decrease debug and trace cost and provide a standard framework across platforms. Partners can integrate their own debug and trace components in CoreSight by complying with the CoreSight architecture specification. 
Learn how CEVA DSP support the CoreSight technology

Today, the CoreSight technology provides on-chip visibility to software and hardware developers in many end products such handsets, mobile devices, set-top boxes and ultra-portable SmartBooks,

Public example of how CoreSight trace is used by Qt developers to optimize Qt performance

Bring values to many users during the life of your SoC

Specified by major OEMs in end products, the CoreSight technology for Cortex-A series processors delivers value to different user groups during all the phases of the SoC life cycle.  

Main user groups   

Main tasks enabled or accelerated by CoreSight technology

Embedded and middleware software developers

  • Driver development and optimization using CPU trace to observe in real-time the execution of the software on the SoC.
  • OS port and debug on new platforms, OS and middleware optimization using CPU trace and software instrumentation
  • Optimization of the platform when running OS

 Application developers   

  • Optimization of applications running on OS either using trace or performance counters
  • Analysis of application impact on SoC (power, performance)

 Product engineer   

  • In the field failure analysis of final product
  • Product debug and maintenance

 Hardware engineer

  •  Debug and optimization of hardware when running software (e.g. memory system debug and analysis, interconnect analysis).

SoC architect   

  • Analysis of existing SoCs based on collected trace in final product
  • Architecture exploration and optimization using existing trace


CoreSight for Cortex-A series is a SoC level solution providing control and visibility for high-end SoC platforms.

Debug

The CoreSight Debug Access Port is a high performance debug access port enabling external debuggers to access cores and internal system busses such memory busses. The DAP provides a combined debug port supporting traditional JTAG and a high performance 2 pin debug interface (Serial Wire Debug)

DAP mode

Number of pins 

Typical frequency

Serial Wire Debug

 2

> 50 MHz

JTAG

4-6

50 MHz

Trace Macrocells and ETM bandwidth

The CoreSight CPU trace macrocells (ETM and PTM), architected to provide highly compressed real-time trace, enabling developers to observe in real-time the software executed on the processors. The main performance characteristics of the CPU trace macrocells are:

Characteristics

Performance 

Trace bandwidth
(average figures)

  • Down to 0.3 bit per instruction for non-cycle accurate instruction trace.

Trace bandwidth generated by ARM CPU trace macrocells will vary depending on the content traced (instruction only vs. data trace), processor, software executed. Please contact ARM for detailed benchmarks.

Operating frequency   

Same as the processor clock and demonstrated by ARM up to 2Ghz, refer to Cortex-A performance for details.

Gate Count 
NAND2.1 equivalent

Gate count for Cortex-A trace macrocell will vary depending on the trace architecture implemented, typically:

  • CPU trace macrocells are between 10 to 20% of the processor gate count.

For detailed benchmarks, please contact ARM.

CoreSight SoC Components, Trace Port & ETB Size

The CoreSight SoC components provide a complete SoC level debug and trace solution with low silicon and pin count overheard. All CoreSight SoC components have been architected to support modern SoC design techniques such  multi-power and clock domains and security.
Main performance characteristics of the CoreSight SoC components are:

 Characteristics 

 Performance

Operating frequency 

400 MHz on 65nm LP (typical)
250 MHz on 90nm
Support for multi clock and power domains

Gate Count
NAND2.1 equivalent
~ 40 kGates for a full debug and multicore tracing (TPIU + ETB)

Trace port size (Trace Port Interface Unit)

By merging all the trace sources in a single trace stream, CoreSight technology enables reducing the number of trace ports to only a single port.

The size of the trace port is a function of the trace bandwidth generated by the trace sources and the nature of the trace, some trace sources create data bursts and may create peak bandwidth leading to a wider trace port.

For reference, benchmarks on Cortex-A9 shows that a 2-bit data trace port running at CPU frequency is in general sufficient to provide in real-time full program trace (non cycle-accurate). This means that a 1 GHz Cortex-A9 processor would need a 4-bit data trace port with a 250 MHz trace clock (DDR)

For detailed benchmarks on trace port for different processors, please contact ARM.

Embedded Trace Buffer (ETB)

When it is not possible to implement a dedicated trace port (e.g. due to severe IO constraints in the final product), traces can be captured on-chip using the CoreSight ETB. Use of the ETB enables high bandwidth trace to capture on the chip. The users based on specific trigger and filter conditions define trace capture.

For detailed benchmarks on ETB sizes for different processors, please contact ARM.

 
For reference, for Cortex-A9 a 4KB ETB can hold trace information for around 125,000 cycles. For multi-processor designs, it is recommended to implement 4KB of ETB memory per CPU.


CoreSight Design Kits consist of the following components:

Component Overview
Debug Access Port

Provide debugger access to the cores and buses in a SoC, across multiple power and clock islands, enabling exceptionally high download speeds direct to memory.

Embedded Cross Trigger
Synchronize debug and trace across multiple cores.
Program Trace Macrocells 
(Cortex-A9)

Non-invasively generate cycle-accurate, instruction trace of ARM processors running at full speed.  
Embedded Trace Macrocells 
(Cortex-A5, Cortex-A8)

Non-invasively generate cycle-accurate, instruction and data trace of ARM processors running at full speed. 
Trace Funnel
Combine multiple trace sources together.
Embedded Trace Buffer
Store trace data on-chip at high rates at 32-bit data width, eliminating the need for dedicated trace port pins or an external trace collection unit.
Trace Port Interface Unit
Transmit trace data off-chip via 2-34 pins at frequencies asynchronous to the core. Instrumentation Trace Macrocell for high level, low bandwidth, software generated trace.
Serial Wire Debug
High performance 2-pin debug port that replaces the 5/6-pin JTAG interface with multi-drop support.
Serial Wire Viewer 
Single pin output for Instrumentation Trace.
Integration Kit
Contain RTL test benches, test vectors and full documentation for easy validation of a designer's own CoreSight subsystem

 

CoreSight Design Kit for Cortex-A processor family available for licensing:

CoreSight Design Kit   Compatible with ARM processor   Trace macrocell included 
 CDK-A5  Cortex-A5  ETM-A5
 CDK-A9  Cortex-A9
(single processor & Multiprocessor)
 PTM-A9
 CDK-A8   Cortex-A8 included part of Cortex-A8


 

Processors

Related Products CoreSight Products Benefits
Cortex-A9 UP & MP    CoreSight Design Kit for Cortex-A9 (CDK-A9) Complete single- & multi-core debug and real-time trace solution for Cortex-A9 processors
Cortex-A8    CoreSight Design Kit for Cortex-A8 (CDK-A8) Complete debug and real-time trace solution for Cortex-A8 processors.
Cortex-A5 UP & MP CoreSight Design Kit for Cortex-A5(CDK-A5)  Complete single- & multi-core debug and real-time trace solution for Cortex-A5 processors.

 

Tools

Related Products

CoreSight Product features 

Benefits
ARM Profiler  CoreSight CPU trace macrocells are used to extract cycle accurate program trace. Generate statistics and coverage results of the code executed. Enables non-intrusive analysis of software performance for virtually unlimited periods of time (days).
RealView Development Suite Professional CoreSight trace macrocells, cross triggering, trace funnels, embedded tace buffers, trace ports, Debug Access Port and Serial Wire Debug. The RealView Debugger supports debug and trace analysis of all ARM CPU processors including synchronized debug of multiple CPUs.
RealView ICE CoreSight debug infrastructure: Serial Wire Debug, Debug Access Port, cross triggering. Run-control unit with advanced debug functionality over JTAG or Serial Wire Debug connection for debug of single- & multi-core system. Using CoreSight DAP, RVI achieves high speed code download up to 1.45 Mbyte/s.
RealView Trace CoreSight trace macrocells, tace funnels and trace port. The RealView Trace capture unit collects high-speed streaming trace from your target system at up to 32 bits @ 480 MHz trace clock.


Getting started with CoreSight

For an overall understanding of CoreSight technology and how to apply CoreSight in your system refer to the CoreSight ™ Technology SystemDesign Guide.

Understanding the CoreSight SoC Components

Refer to the CoreSight SoC page or read the CoreSight™ Components Technical Reference Manual

 
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