Part of the CoreSight solution, ARM provides a comprehensive set of real-time trace macrocells:
- ARM processor real-time trace macrocells (ETM / PTM) to observe how the software executes on the ARM processor(s).
- Instrumentation trace macrocell for high level software instrumentation (print type debug, OS and application events)
- Bus trace macrocell to make bus information visible that you cannot infer from core trace.
Why Embedded Trace Macrocells?
When it comes to debug or to optimize an embedded system, embedded developers have two main options available to them:
- Conventional debug: typically setting breakpoints and/or watch points to halt the processing unit and from there use a debug connection to examine or modify register or memory and single-step to understand how the program works.
While enabling developers to control the execution and debug their code, conventional debug has several disadvantages:
- Intrusive: debug halters the behavior of the system
- Requirement to stop the processor, for some applications it may not be possible to stop the processor (e.g. hard-disk, automotive, …)
- Non real-time: cannot be used to debug software operating real-time.
- No performance visibility: cannot observe software performance.
- Real-time trace: when the system is running, trace macrocells collect instruction and / or data transfer, compress this information and deliver off-chip in real-time or on-chip for post processing.
Trace is post-merged with source code in development workstation for later analysis.
The CoreSight Embedded trace macrocells enable developers to accelerate their product developments and deliver high quality optimized software by analyzing in real-time how the software operates on the platform.
ETM and PTM main features and benefits are:
|Trace the core at full speed with zero performance overhead||Trace and debug your system executing in real-time|
|Cycle-accurate trace||Collect vital timing on program execution for performance optimizations and ‘always-in-time’ code verification|
|Extensive sequential trigger logic & on-chip filtering conditions control which data is captured||Capture program activity around the event you want to look at
View trace over longer elapsed time
|Very high trace data compression (~ 0.4 bit trace per instruction for Cortex-A9)||More visibility requiring less pins or smaller trace buffers|