Login

CoreSight Trace Macrocells

CoreSight Trace Macrocells Image (View Larger CoreSight Trace Macrocells Image)
CoreSight™ trace macrocells provide non-intrusive, comprehensive visibility across an SoC.
  • Embedded Trace Macrocell ™ (ETM) for non-intrusive, cycle accurate program and data trace of ARM processors
  • Program Trace Macrocell (PTM) for program flow trace of Cortex-A9
  • Instrumentation Trace Macrocell (ITM) for high level software view
  • AHB Trace Macrocell  (HTM) for performance and functional debug

Partner specific trace macrocells integrate easily into the CoreSight system by complying with the CoreSight architecture specification.

 


As geometry shrinks and SoC package size remains constant or gets smaller, driven by cost, dedicated real-time trace modules are required to provide on-chip visibility.

Part of the CoreSight solution, ARM provides a comprehensive set of real-time trace macrocells:

  • ARM processor real-time trace macrocells (ETM / PTM) to observe how the software executes on the ARM processor(s).
  • Instrumentation trace macrocell for high level software instrumentation (print type debug, OS and application events)
  • Bus trace macrocell to make bus information visible that you cannot infer from core trace.

Why Embedded Trace Macrocells?

When it comes to debug or to optimize an embedded system, embedded developers have two main options available to them:

  1. Conventional debug: typically setting breakpoints and/or watch points to halt the processing unit and from there use a debug connection to examine or modify register or memory and single-step to understand how the program works.

    While enabling developers to control the execution and debug their code, conventional debug has several disadvantages:
    • Intrusive: debug halters the behavior of the system
    • Requirement to stop the processor, for some applications it may not be possible to stop the processor (e.g. hard-disk, automotive, …)
    • Non real-time: cannot be used to debug software operating real-time.
    • No performance visibility: cannot observe software performance.
  2. Real-time trace: when the system is running, trace macrocells collect instruction and / or data transfer, compress this information and deliver off-chip in real-time or on-chip for post processing.
    Trace is post-merged with source code in development workstation for later analysis.

The CoreSight Embedded trace macrocells enable developers to accelerate their product developments and deliver high quality optimized software by analyzing in real-time how the software operates on the platform.
ETM and PTM main features and benefits are:

Main Feature

Main Benefits

Trace the core at full speed with zero performance overhead  Trace and debug your system executing in real-time
Cycle-accurate trace  Collect vital timing on program execution for performance optimizations and ‘always-in-time’ code verification 
Extensive sequential trigger logic & on-chip filtering conditions control which data is captured  Capture program activity around the event you want to look at
View trace over longer elapsed time 
Very high trace data compression (~ 0.4 bit trace per instruction for Cortex-A9)  More visibility requiring less pins or smaller trace buffers 


CPU Trace Macrocells benchmarks

For ETM benchmark considerations please refer to:


CPU Trace Macrocells™ (ETM / PTM)

Embedded Trace Macrocells™ (ETM) and Program Trace Macrocells™ (PTM) provide comprehensive debug and trace facilities for ARM processors. They allow capture of information on the processor both before and after a specific event, while adding no burden to the processor's performance, while the processor runs at full speed.

The ARM CPU trace macrocell family comprises the CoreSight ETM and PTM for Cortex™ processors (A, R and M series) and the ETM11™, ETM9™, ETM7™.

The Embedded Trace Macrocell can be configured in software to capture only select trace information and only after a specific sequence of conditions, see Table 1.

The CoreSight SoC infrastructure enables the compressed trace data to either be captured on-chip using an Embedded Trace Buffer or to be read from the chip by an external trace port analyzer (such the RealView Trace unit) without interrupting, or effecting, the processor. More details on CoreSight SoC components.

CoreSight ETMs & PTM, designed for use both standalone and within a multi-core environment using the features of the CoreSight Design Kits, allow the developer to view simultaneous, correlated trace from multiple, asynchronous cores.

Table 1 - ETM Features

Feature  #
Address Comparators  8
Data Comparators  2
Address Range Comparators   4
16-bit Counters   2
Three-stage Sequencer   1
External Inputs   4
External Outputs  2*

Notes
Areas are from trial synthesis, post layout.
ETM7 (medium) has only one external output.

Embedded Trace Macrocells (ETM)

ETM macrocells provide real-time instruction trace and data trace for the ARM microprocessor. The ETM generates information that trace software tools use to reconstruct the execution of all or part of a program.

Program Trace Macrocell (PTM)

The PTM is a module that performs real-time instruction flow tracing based on the Program Flow Trace (PFT) architecture. The PTM generates information that trace tools use to reconstruct the execution of all or part of a program.

Instrumentation Trace Macrocell (ITM)

The CoreSight ITM block is a software application driven trace source. Supporting code generates SoftWare Instrumentation Trace (SWIT). In addition, the block provides a coarse-grained timestamp functionality.

The main uses for this block are to:

  • support printf style debugging
  • trace OS and application events
  • emit diagnostic system information.

AHB Trace Macrocell (HTM)

The HTM makes bus information visible that you cannot infer from core trace using an ETM:

  • An understanding of multi-layer bus utilization.
  • Software debug. For example, visibility of access to memory areas and data accesses.
  • Bus event detection for trace trigger or filters, and for bus profiling.

The HTM provides address and data trace information about AHB buses. The information from an HTM, used with the debugger, enables easy, accurate debugging on AHB-based embedded systems. The HTM provides extensive resources for event recognition to generate trigger events. The HTM generates trace data for output through the AMBA Trace Bus (ATB). The trace debug function is non-intrusive. HTM can be controlled using an APB (AMBA v3) interface.


 

Processors

Related Products

CoreSight Products

Benefits

ARM7TDMI, ARM7TDMI-S, ARM720TSC100 ETM7 Full cycle accurate, non-invasive, instruction and data trace of a single ARM7 processor.
ARM920T,  ARM922T, ARM9TDMI, SC200 ETM9     Full cycle accurate, non-invasive, instruction and data trace of a single ARM9 processor.
ARM926EJ-S,  ARM946E-S,  ARM966E-S,  ARM968E-S,  ARM7EJ-S  CoreSight ETM9  Full cycle accurate, non-invasive, instruction and data trace of ARM9E processors. CoreSight compatible for multi-core debug and trace.
ARM1136J(F)-S,  ARM1156T2(F)-S,  ARM1176JZ(F)-S, ARM11 MPCore  CoreSight ETM11 Full cycle accurate, non-invasive, instruction and data trace of ARM11 processors. CoreSight compatible for multi-core debug and trace.
Cortex-R4 CoreSight ETM-R4     Full cycle accurate, non-invasive, instruction and data trace of Cortex-R4 processors. CoreSight compatible for multi-core debug and trace.
Cortex-A5 CoreSight ETM-A5    Full cycle accurate, non-invasive, instruction and data trace of Cortex-A5 processors. CoreSight compatible for multi-core debug and trace, with global time stamping for asynchronous trace correlation.
Cortex-A9 CoreSight PTM-A9 Non-invasive, program flow trace of Cortex-A9 processors. CoreSight compatible for multi-core debug and trace, with global time stamping for asynchronous trace correlation.
Cortex-A8 ETM included with core (optional in synthesizable core) Cycle accurate, non-invasive, instruction and data address trace of Cortex-A8 processors. CoreSight compatible for multi-core debug and trace.
Cortex-M3, SC300

ETM included with core (optional)    

ATB Async Bridge

ATB Upsizer

Non-invasive, instruction trace of Cortex-M3 and SC300 processors. CoreSight compatible for multi-core debug and trace.

ATB Async Bridge and Upsizer for optimal integration in higher frequency multi-core SoCs.


 
» 
Powered 5607
Go Left
Go Right

Maximise


Cookies

We use cookies to give you the best experience on our website. By continuing to use our site you consent to our cookies.

Change Settings

Find out more about the cookies we set