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CoreLink Network Interconnect for AMBA AXI

CoreLink Network Interconnect for AMBA AXI Image (View Larger CoreLink Network Interconnect for AMBA AXI Image)
Massive growth in system integration places on-chip communication at the center of system performance.

CoreLinkThe ARM  CoreLink™ NIC-400 Network Interconnect provides a fully configurable, hierarchical, low latency, low power connectivity for AMBA® 4 AXI4™, AMBA 3 AXI3™, AHB™-Lite and APB™ components. The NIC-400 adds new features over the NIC-301 such as advanced power management with heirarchical clock gating and options for Thin Links to reduce routing congestion and QoS Virtual Networks to prevent blocking.

 


Configurable by design

  • The CoreLink NIC-400 Network Interconnect is a highly configurable IP that can be optimized to suit the requirements of a complex SoC using the AMBA protocols. The QoS-400 Advanced Quality of Service option provides dynamic bandwidth or latency controlled regulators for the efficient and intelligent management of traffic in complex multi-master designs.
  • New with the NIC-400 is the QVN-400 QoS Virtual Networks option to prevent cross-stream or head-of-line blocking through a priority driven allocation of buffer space to different virtual channels in both the interconnect and the dynamic memory controller (DMC-400).
  • The TLX-400 Thin Links option for NIC-400 packetized AXI4 connections, for transmission between switches over fewer signals to reduce wiring congestion and ease timing closure

Example NIC-301 implementation

Coherency between high performance CPU clusters, GPU and other masters

Design and build a network of AMBA interconnect switches 

  • A ‘must’ for small geometries and increasing numbers of IP cores
  • Each switch can be configured for different bus widths from 32 to 256 bits wide, and for different clock domains with automatic insertion bus width and clock conversion bridging

Optimized for low latency

  • The latest release includes new bridges with reduced arbitration & translation latency across clock domains, data widths and AMBA protocols

Advanced timing closure options for high frequency

  • The user has full control of register placement allowing fine grain tuning in the trade-off between clock speed and latency
  • Timing closure can be aided by per-channel and per-direction timing closure to isolate long paths

Data packing & buffering for efficient communication

  • Configurable address and data buffers can be inserted to reduce translation stall
  • Up-sizing bridges efficiently pack data when going from narrow to wide data paths

Integrated with AMBA design tools

  • New user interface configures a network of interconnect switches, with full control of port types (AXI, AHB and APB), bus width and clock domain selection

Interconnect performance in terms of raw clock speed depends on many factors including the configuration, size and the system components it is connected to, and of course the silicon technology it is implemented with. An important feature of the CoreLink Network Interconnect is the ability to configure and enable pipeline register stages at various points in the design. This allows a fine grain control in the trade-off between clock speed, and latency.

Low power is also important to ARM, and the CoreLink Network Interconnect is no exception. The RTL is optimized to make extensive use of automated clock gate insertion by synthesis tools. Implementation trials have shown that as many as 95% of the flops are clock gated when idle.

Small interconnect switches with few ports are faster than large switches with many ports, therefore the latest CoreLink Network Interconnect allows for the generation and stitching of a network of small switches. This network of switches strategy improves the overall performance for a system. In addition, each switch can operate on its own clock domain. Defined to be asynchronous, they allow easier timing closure across a large silicon die.


Network of interconnects (NIC-400, NIC-301)

An instance of the product is a network of interconnects. Creating complex systems is easy and configuration options checked for consistency

  • Topology design to match floor plan & dataflow requirements
  • Interface-and-switch architecture optimizes logic between interconnects for lower gate count

Virtual networks to prevent blocking

An option (QVN-400) uses priority controlled allocation of buffer space in the NIC-400 interconnect and DMC-400 memory controller to prevent cross-line and head-of-line blocking throughout the entire path form processors to memory.

Thin Links

An option (TLX-400) available for the NIC-400 to reduce routing between AXI switches

Long Bursts in AMBA 4 AXI4

The new NIC-400 adds support for long bursts to improve the efficiency of media streaming

Lower power with hierarchical clock gating

Added with the NIC-400 to reduce idle power by over 90%.

Optimized translation latency

Only one latency penalty for any combination of clock, data width and protocol translations

Single cycle arbitration

Arbitration has single-cycle throughput and single-cycle switching so that there are no pipeline bubbles

Global dynamic QoS

QoS information travels dynamically with the transaction through the network of interconnects, for distributed arbitration in a network structure

Enhanced buffering to reduce stall

Buffering can be configured in each channel at crossing points to accept transactions so that stall is not induced in critical communication paths

Multiple outstanding transactions through downsizer

When reducing data width, a configurable number of outstanding transactions can be processed simultaneously

Up-sizer packs data into wide bus

Narrow data efficiently packed onto the wide data path

Internally programmable

Programming of the network is address mapped inside of the network so that no external loop-back connections are necessary

System-level address map

System-level address map described independently of network design.  Masters can have independent address maps

Extended timing closure options

timing closure options per AXI channel & per direction (forwards, reverse)

  • Either side of network interface
  • At translation boundary
  • Between switches
  • Post-arbitration
  • Intra-arbitration

256-bit maximum data width

256-bit maximum data width, with translations to- and from- 32-bit data

Multi-region slave support

Decoding of sparse slaves is precise, and errors are reported from the interconnect

Write-data release control

In network interfaces, the release of write data can be programmed to remove bubbles from the data path when data is not received in consecutive cycles


AMBA Interconnect Products

 Related Products

Benefits


 AMBA Design Kit (ADK)
AMBA AHB Processors including Cortex-M family
 Use the AMBA Design Kit for systems with only AHB components (no AXI)

CoreLink Network Interconnect 
(NIC-400, QoS-400, QVN-400, TLX-400, NIC-301, QoS-301)

Cortex-A & Cortex-R processors

Optimized for low latency, increasing system performance for Cortex processor-based SoCs.

Mali graphics and video processors 

Delivers high bandwidth with high frequency, efficient operation for best multi-media performance.

AMBA Designer (ADR-301) 

The design environment for configuring AMBA system IP and connecting them together with Cortex and Mali processors.

Verification & Performance Exploration (VPE-301)

Enables fast, accurate performance analysis of AMBA AXI-based systems.

CoreLink Dynamic Memory Controllers (DMC-400, MC-34x) 

Delivers a combination of low-latency and high-bandwidth data path to main memory for systems that include ARM Cortex & Mali processors.


ARM Connected Community

CoreLink NIC-400 related blogs, discussions, technical content

Models

The NIC-400 model from Carbon Design Systems is compiled directly from ARM's register transfer level (RTL) code and maintains 100% functional accuracy. The model integrates directly with Carbon’s SoC Designer Plus virtual prototype. This enables designers to perform accurate architectural analysis, performance optimization and pre-silicon firmware debug.

Using Synopsys' Platform Architect MCO and SBL-400 SystemC model, system designers can explore CoreLink NIC-400 configuration parameters at run-time, enabling efficient simulation sweeping, data collection, sensitivity analysis, root cause analysis, and performance and cost optimization from thousands of configurations.

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FAQs & Knowledge Articles

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