CoreLink DMC-400 Dynamic Memory Controller
Optimized and efficient access to the DRAM is critical to the performance of any SoC. As the number of processing elements on a chip increases, the demand for data increases. As the DRAM technology evolves, the frequency of operation rises, and the complexity of making best use of the DRAM increases. Managing the differing demands of multiple processing elements while trying to make optimum use of DRAM is the challenge faced by a Dynamic Memory Controller.
The CoreLink DMC-400 is ARM's fourth generation of Memory Controller. CoreLink DMC-400 has been designed to meet the needs of different masters in the system while trying to achieve maximum bandwidth from the DRAM. CoreLink DMC-400 is a key part of ARM's End-to-End Quality of Service (QoS) scheme which includes features distributed across both Interconnect and Memory Controllers.
The CoreLink DMC-400 has an advanced QoS based scheduling and arbitration algorithm. QoS values defined by the system are used to re-order transations to be sent to memory. The DMC arbitration uses bank and row status to aggressively re-order transactions to optimise both bank parallelism and in row hits.
The CoreLink DMC-400 has been specified, designed and validated in conjunction with ARM's CoreLink-400 System IP.